US5132685A
Expired / Lapsed
US
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Built-in self test for analog to digital converters
Assignee: Nokia Bell Labs
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Filing: 1991-08-09
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Granted: 1992-07-21
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Expires: 2011-08-09
Abstract
Abstract An integrated circuit having an analog-to-digital converter includes built-in self-test (BIST) circuitry. The BIST circuitry checks for monotonicity, and typically also that all possible codes are present, by applying a ramp voltage to the A/D input, while a state machine monitors the output. The state machine can check to ensure that the output increases by only one least significant bit (LSB) each time the output changes. A counter may be checked at the end of the test, to ensure that all the possible codes are obtained. The BIST circuitry may be activated, and the results monitored, through package terminals after the chip is packaged, thereby allowing for boundary scan testing. The inventive technique may be used to save testing costs during manufacture. In addition, system diagnostics in the field can become more cost effective.
Inventors
- 👤 Michael R. DeWitt
- 👤 George F. Gross, Jr.
- 👤 R. Ramachandran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:05
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1071; H03M1/108; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318502; H03M1/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
186 words
An integrated circuit including an analog to digital converter that converts an analog signal into an n-bit digital output code, characterized in that said integrated circuit further includes self-test means comprising: means for providing a monotonic ramp voltage input signal during a test; and finite state means for determining whether successive digital output codes differ from the previous value by less than a specified amount during said test, wherein said finite state means comprises: a present code register for storing a given n-bit output code; a previous code register for storing the n-bit output code previous to said given output code; and first comparator means for comparing the contents of the present and previous code registers in order to determine whether a code immediately following any given code differs from the given code by more than one least significant bit, in which case a fail signal is generated, wherein said finite state means further determines whether any given code reverts one least significant bit to a previous code in each of two conversions immediately following the given code, in which case a fail signal is generated.
Claim 2
Dependent Claim
186 words
An integrated circuit including an analog to digital converter that converts an analog signal into an n-bit digital output code, characterized in that said integrated circuit further includes self-test means comprising: means for providing a monotonic ramp voltage input signal during a test; and finite state means for determining whether successive digital output codes differ from the previous value by less than a specified amount during said test, wherein said finite state means comprises: a present code register for storing a given n-bit output code; a previous code register for storing the n-bit output code previous to said given output code; and first comparator means for comparing the contents of the present and previous code registers in order to determine whether a code immediately following any given code differs from the given code by more than one least significant bit, in which case a fail signal is generated, wherein said finite state means further determines whether any given code reverts one least significant bit to a previous code in each of two conversions immediately following the given code, in which case a fail signal is generated.
Claim 3
Dependent Claim
90 words
The integrated circuit of claim 1 wherein said self-test means further comprises all code means for determining whether all 2 n digital output codes are produced by said converter during said test, wherein said all code means comprises: a counter means that is incremented by said first comparator means when the difference between the contents of said present code register and said previous code register is one least significant bit having a given sign; and a second comparator means for comparing the contents of said counter with an expected count.
Claim 4
Dependent Claim
46 words
The integrated circuit of claim 1 wherein said self-test means further comprises linearity means for counting the number of conversions for each of the codes, and providing a fail signal when the number of conversions for at least one code is outside of a desired limit.
Claim 5
Dependent Claim
13 words
The integrated circuit of claim 1 wherein said fail signal terminates said test.
Claim 6
Dependent Claim
245 words
An electronic system comprising a multiplicity of integrated circuits at least a given one of which has test means for performing a built-in self-test, wherein said system includes means for activating said test means, and further includes means for receiving the test results produced by said test means, with the given integrated circuit including an analog to digital converter that converts an analog signal into an n-bit digital output code, characterized in that said test means comprises: means for providing a monotonic ramp voltage input signal to said analog to digital converter during a test; and finite state means for determining whether successive digital output codes from said analog to digital converter differ from the previous value by less than a specified amount during said test, wherein said finit state means comprises: a present code register for storing a given n-bit output code; a previous code register for storing the n-bit output code previous to said given output code; and first comparator means for comparing the contents of the present and previous code registers in order to determine whether a code immediately following any given code differs from the given code by more than one least significant bit, in which case a fail signal is generated, wherein said finite state means further determines whether any given output code reverts one least significant bit to a previous code in each of two conversions immediately following the given code, in which case a fail signal is generated.
Claim 7
Dependent Claim
245 words
An electronic system comprising a multiplicity of integrated circuits at least a given one of which has test means for performing a built-in self-test, wherein said system includes means for activating said test means, and further includes means for receiving the test results produced by said test means, with the given integrated circuit including an analog to digital converter that converts an analog signal into an n-bit digital output code, characterized in that said test means comprises: means for providing a monotonic ramp voltage input signal to said analog to digital converter during a test; and finite state means for determining whether successive digital output codes from said analog to digital converter differ from the previous value by less than a specified amount during said test, wherein said finit state means comprises: a present code register for storing a given n-bit output code; a previous code register for storing the n-bit output code previous to said given output code; and first comparator means for comparing the contents of the present and previous code registers in order to determine whether a code immediately following any given code differs from the given code by more than one least significant bit, in which case a fail signal is generated, wherein said finite state means further determines whether any given output code reverts one least significant bit to a previous code in each of two conversions immediately following the given code, in which case a fail signal is generated.
Claim 8
Dependent Claim
90 words
The electronic system of claim 5 wherein said test means further comprises all code means for determining whether all 2 n digital output codes are produced by said converter during said test, wherein said all code means comprises: a counter means that is incremented by said first comparator means when the difference between the contents of said present code register and said previous code register is one least significant bit having a given sign; and a second comparator means for comparing the contents of said counter with an expected count.
Claim 9
Dependent Claim
46 words
The electronic system of claim 5 wherein said test means further comprises linearity means for counting the number of conversions for each of the codes, and providing a fail signal when the number of conversions for at least one code is outside of a desired limit.
Claim 10
Dependent Claim
13 words
The electronic system of claim 5 wherein said fail signal terminates said test.
References Cited (Backward Citations)
US3603772A
Cited
US3816813A
Cited
US4352160A
Cited
US4354177A
Cited
US4539683A
Cited
JPS61137429A
Cited
DD247334A1
Cited
DD247384A1
Cited
US4872168A
Cited
US4827259A
Cited
US4947106A
Cited
US4897650A
Cited
US4908621A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |