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US5130671A Expired / Lapsed US ⏱️ 0.0 years remaining

Phase-locked loop frequency tracking device including a direct digital synthesizer

Assignee: Boeing Co
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Filing: 1990-12-26
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Granted: 1992-07-14
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Expires: 2010-12-26
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Abstract

Abstract Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to the accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency. In a second embodiment, the DC representative phase signal is applied to an analog-to-digital converter (364) which produces an N-bit word representative of the phase difference. The change in phase alters the digital output of the analog-to-digital converter (364) which in turn is applied to the accumulator (376) of a direct digital synthesizer (370). By this invention, very wide band tracting is capable with a single phase-locked loop, thus limiting the hardware and cost.

Inventors

  • 👤 Iradj Shahriary
  • 👤 Kevin M. McNab

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 17:19
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0994; H03L7/10; H03L7/107; H03L7/12

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 86 words
A phase-locked loop comprising: a phase detector for comparing the phase of an input signal having a time varying frequency with a return signal and for generating a DC magnitude signal representative of the comparison; an analog-to-digital converter for receiving the DC magnitude signal from the phase detector and generating a digital magnitude signal in response thereto; and a direct digital synthesizer for receiving the digital magnitude signal from the analog-to-digital converter and for generating in response thereto an output signal representative of the input signal.
Claim 2
Dependent Claim 86 words
A phase-locked loop comprising: a phase detector for comparing the phase of an input signal having a time varying frequency with a return signal and for generating a DC magnitude signal representative of the comparison; an analog-to-digital converter for receiving the DC magnitude signal from the phase detector and generating a digital magnitude signal in response thereto; and a direct digital synthesizer for receiving the digital magnitude signal from the analog-to-digital converter and for generating in response thereto an output signal representative of the input signal.
Claim 3
Dependent Claim 18 words
The phase-locked loop of claim 1 further comprising means for applying a sampling signal to the analog-to-digital converter.
Claim 4
Dependent Claim 30 words
The phase-locked loop of claim 2 wherein the direct digital synthesizer includes an accumulator, for receiving the digital magnitude signal from the analog-to-digital converter and a substantially constant clocking frequency.
Claim 5
Dependent Claim 62 words
The phase-locked loop of claim 3 wherein the direct digital synthesizer further includes a sine look-up ROM and a digital-to-analog converter, the ROM receiving a phase output signal from the accumulator and converting it to a digital amplitude output signal and the digital-to-analog converter converting the digital amplitude output signal from the ROM to the output signal representative of the input signal.
Claim 6
Dependent Claim 36 words
The phase-locked loop of claim 1 further comprising a program counter, for applying a sweeping signal to the direct digital synthesizer to adjust the synthesizer output signal until it is substantially representative of the input signal.
Claim 7
Dependent Claim 20 words
The phase-locked loop of claim 5 further comprising a digital limiter, for limiting the sweep range of the program counter.
Claim 8
Dependent Claim 21 words
The phase-locked loop of claim 1 further comprising a loop filter, for removing high frequency signals from the DC magnitude signal.
Claim 9
Independent Claim 56 words
A method of tracking a carrier frequency comprising the steps of: applying an input carrier signal to a phase detector; applying an output of the phase detector to an analog-to-digital converter; applying an output of the analog-to-digital converter to a direct digital synthesizer; and applying an output of the direct digital synthesizer to the phase detector.
Claim 10
Independent Claim 56 words
A method of tracking a carrier frequency comprising the steps of: applying an input carrier signal to a phase detector; applying an output of the phase detector to an analog-to-digital converter; applying an output of the analog-to-digital converter to a direct digital synthesizer; and applying an output of the direct digital synthesizer to the phase detector.
Claim 11
Dependent Claim 25 words
The method of claim 8 wherein the step of applying an output to the analog-to-digital converter includes applying a sampling signal to the analog-to-digital converter.
Claim 12
Dependent Claim 32 words
The method of claim 9 wherein the step of applying an output to the direct digital synthesizer includes applying said output to an accumulator which also receives a substantially constant clocking signal.
Claim 13
Dependent Claim 40 words
The method of claim 10 wherein the step of applying an output to the direct digital synthesizer includes applying an output of the accumulator to a sine look-up ROM and applying an output of the ROM to a digital-to-analog converter.
Claim 14
Dependent Claim 26 words
The method of claim 8 further comprising the step of applying the output of the analog-to-digital converter and a digital sweep signal to a program counter.
Claim 15
Dependent Claim 27 words
The method of claim 8 further comprising the step of applying the output of the analog-to-digital converter and a digital limit set signal to a digital limiter.
Claim 16
Dependent Claim 21 words
The method of claim 8 further comprising the step of applying the output of the phase detector to a loop filter.
Claim 17
Independent Claim 69 words
A method of tracking a carrier frequency comprising the steps of: comparing the phase of an input signal with the phase of a return signal; generating a digital magnitude signal in response to the comparison; applying the magnitude signal to a direct digital synthesizer for generating an output signal representative of the input signal in response to the magnitude signal; and employing the output signal as the return signal.
Claim 18
Independent Claim 69 words
A method of tracking a carrier frequency comprising the steps of: comparing the phase of an input signal with the phase of a return signal; generating a digital magnitude signal in response to the comparison; applying the magnitude signal to a direct digital synthesizer for generating an output signal representative of the input signal in response to the magnitude signal; and employing the output signal as the return signal.
Claim 19
Dependent Claim 34 words
The method of claim 15 further comprising the step of sweeping the direct digital synthesizer through a range of frequencies to adjust the output signal until it is substantially representative of the input signal.

References Cited (Backward Citations)

US4568888A Cited
US4577163A Cited
US4855683A Cited
US4951004A Cited
US4965533A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-07-14 1996-01-13 1996-07-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-07-14 2000-01-13 2000-07-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-07-14 2004-01-13 2004-07-14 $7700.00 Window Closed / Lapsed

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