Switching mode power supplies with controlled synchronization

Claim 2

Power supply apparatus comprising: a) a first, fixed-frequency, pulse width modulated DC power supply including (i) a first power switch, and (ii) circuit first means for controlling on-time, and thus duty cycle, of said first power switch so as to maintain voltage regulation of the output of said first power supply, the maximum allowable duty cycle of said first switch being 50 percent; b) a second, fixed-frequency, pulse width modulated DC power supply including (i) a second power switch, and (ii) circuit second means for controlling on-time, and thus duty cycle, of said second power switch so as to maintain voltage regulation of the output of said second power supply, the maximum allowable duty cycle of said second switch being 50 percent; and, c) circuit third means, connected to said first and second supplies, for (i) causing synchronization of said first and second supplies in such a way that any overlap of the on-times of the first and second power switches is prevented during synchronization for all allowable values of the two duty cycles, and (ii) automatically disabling the synchronization of said first and second supplies in response to an output undervoltage condition of at least one of the first and second supplies; d) the on-times of said first and second switches, and thus the duty cycles thereof, being capable of being unequal to one another during synchronization.

Claim 3

Apparatus as defined in claim 1 wherein the automatic disabling of synchronization occurs in response to an output undervoltage condition of the first supply, and also occurs in response to an output undervoltage condition of the second supply.

Claim 4

Apparatus as defined in claim 2 wherein said automatic disabling of synchronization is deactivated when no undervoltage condition remains, so that the synchronization is reinstated.

Claim 5

Apparatus as defined in claim 3 wherein said circuit first means includes a first clock, and said circuit second means includes a second clock.

Claim 6

Apparatus as defined in claim 4 wherein the on-time of the first power switch is less than or equal to the period of the first clock and wherein the on-time of the second power switch is less than or equal to the period of the second clock.

Claim 7

Apparatus as defined in claim 5 wherein, when synchronization is enabled, the periods of the first and second clocks are the same, and the beginning of the on-time of the first power switch is separated in time from the beginning of the on-time of the second power switch by the period of the first clock.

Claim 8

Apparatus as defined in claim 6 wherein, the power supply apparatus includes a single unregulated DC source which contributes to both the first supply output and the second supply output.

Claim 9

Apparatus as defined in claim 4 wherein, when synchronization is enabled, the periods of the first and second clocks are the same, and the beginning of the on-time of the first power switch is separated in time from the beginning of the on-time of the second power switch by the period of the first clock.

Claim 10

Power supply apparatus comprising: a) a first, fixed-frequency, pulse width modulated DC power supply including (i) a first power switch, and (ii) circuit first means for controlling on-time, and thus duty cycle, of said first power switch so as to maintain voltage regulation of the output of said first power supply, the maximum allowable duty cycle of said first switch being 50 percent, said circuit first means including (I) a master clock means for outputting a master timing signal having a master period and (II) a master divide-by-two circuit for outputting a divided master timing signal whose period is twice the master period; b) a second, fixed-frequency, pulse width modulated DC power supply including (i) a second power switch, and (ii) circuit second means for controlling on-time, and thus duty cycle, of said second power switch so as to maintain voltage regulation of the output of said second power supply, the maximum allowable duty cycle of said second switch being 50 percent, said circuit second means including (I) a slave clock means for outputting a slave timing signal having a slave period and (II) a slave divide-by-two circuit for outputting a divided slave timing signal whose period is twice the slave period; c) circuit third means, connected to the master clock means and the master and slave divide-by-two circuits, for causing synchronization pulses, of a period equal to the master period, to be delivered to the slave clock means such that the slave period becomes equal to the master period, and for causing the slave divide-by-two circuit to be reset so that the divided master and divided slave timing signals are 180° out of phase, and so that the beginning of the first power switch on-time is 180° out of phase with the beginning of the second power switch on-time whereby overlapping of power switch on-times is prevented during synchronization for all allowable values of the two duty cycles; and d) circuit fourth means, connected to said first and second supplies, and to said third means, for automatically disabling, when an undervoltage condition is detected on the output of either the first or second supplies, (i) the synchronization pulses to the slave clock means and (ii) the resetting of the slave divide-by-two circuit; e) the on-times of said first and second switches, and thus the duty cycles thereof, being capable of being unequal to one another during synchronization.

Claim 11

Power supply apparatus comprising: a) a first, fixed-frequency, pulse width modulated DC power supply including (i) a first power switch, and (ii) circuit first means for controlling on-time, and thus duty cycle, of said first power switch so as to maintain voltage regulation of the output of said first power supply, the maximum allowable duty cycle of said first switch being 50 percent, said circuit first means including (I) a master clock means for outputting a master timing signal having a master period and (II) a master divide-by-two circuit for outputting a divided master timing signal whose period is twice the master period; b) a second, fixed-frequency, pulse width modulated DC power supply including (i) a second power switch, and (ii) circuit second means for controlling on-time, and thus duty cycle, of said second power switch so as to maintain voltage regulation of the output of said second power supply, the maximum allowable duty cycle of said second switch being 50 percent, said circuit second means including (I) a slave clock means for outputting a slave timing signal having a slave period and (II) a slave divide-by-two circuit for outputting a divided slave timing signal whose period is twice the slave period; c) circuit third means, connected to the master clock means and the master and slave divide-by-two circuits, for causing synchronization pulses, of a period equal to the master period, to be delivered to the slave clock means such that the slave period becomes equal to the master period, and for causing the slave divide-by-two circuit to be reset so that the divided master and divided slave timing signals are 180° out of phase, and so that the beginning of the first power switch on-time is 180° out of phase with the beginning of the second power switch on-time whereby overlapping of power switch on-times is prevented during synchronization for all allowable values of the two duty cycles; and d) circuit fourth means, connected to said first and second supplies, and to said third means, for automatically disabling, when an undervoltage condition is detected on the output of either the first or second supplies, (i) the synchronization pulses to the slave clock means and (ii) the resetting of the slave divide-by-two circuit; e) the on-times of said first and second switches, and thus the duty cycles thereof, being capable of being unequal to one another during synchronization.

Claim 12

Power supply apparatus comprising: a) a first, fixed-frequency, pulse width modulated power supply including (i) a first power switch, and (ii) circuit first means for controlling on-time, and thus duty cycle, of said first power switch so as to maintain voltage regulation of the output of said first power supply, the maximum allowable duty cycle of said first switch being 50 percent, said circuit first means including (I) a master clock means for outputting a master timing signal having a master period and (II) a master divide-by-two circuit for outputting a divided master timing signal whose period is twice the master period; b) a second, fixed-frequency, pulse width modulated power supply including (i) a second power switch, and (ii) circuit second means for controlling on-time, and thus duty cycle, of said second power switch so as to maintain voltage regulation of the output of said second power supply, the maximum allowable duty cycle of said second switch being 50 percent, said circuit second means including (I) a slave clock means for outputting a slave timing signal having a slave period and (II) a slave divide-by-two circuit for outputting a divided slave timing signal whose period is twice the slave period; c) circuit third means, connected to the master clock means and the master and slave divide-by-two circuits, for causing synchronization pulses, of a period equal to the master period, to be delivered to the slave clock means such that the slave period becomes equal to the master period, and for causing the slave divide-by-two circuit to be reset so that the divided master and divided slave timing signals are 180° out of phase, and so that the beginning of the first power switch on-time is 180° out of phase with the beginning of the second power switch on-time; and d) circuit fourth means, connected to said first and second supplies, and to said third means, for automatically disabling, when an undervoltage condition is detected on the output of either the first or second supplies, (i) the synchronization pulses to the slave clock means and (ii) the resetting of the slave divide-by-two circuit; e) the on-times of said first and second switches being capable of being different from one another during synchronization; the circuit third and fourth means comprising: first and second AND gates; first and second inverters; first and second undervoltage detectors; a logic OR circuit comprising two suitably interconnected transistors; and a diode; said first AND gate connected to the outputs of the master divide-by-two circuit and the slave divide-by-two circuit; said first inverter connected to the output of the master clock means; said diode connected to the output of the first inverter; said second inverter connected to the output of the diode; said second AND gate connected to the outputs of the first AND gate and the second inverter; said second AND gate having output connected to reset the slave divide-by-two circuit; the diode having output connected for effecting said synchronization pulses; said first and second undervoltage detectors having inputs connected to the outputs of said first and second supplies, respectively; said logic OR circuit connected to the outputs of the first and second undervoltage detectors and for outputting, to the junction of the diode and the second inverter, whenever either or both of the first and second undervoltage detectors detects a low voltage condition on its input, a signal preventing both the synchronization of the clocks and the resetting of the slave divide-by-two circuit.

Claim 13

Power supply apparatus comprising: a) a first, fixed-frequency, pulse width modulated power supply including (i) a first power switch, and (ii) circuit first means for controlling on-time, and thus duty cycle, of said first power switch so as to maintain voltage regulation of the output of said first power supply, the maximum allowable duty cycle of said first switch being 50 percent, said circuit first means including (I) a master clock means for outputting a master timing signal having a master period and (II) a master divide-by-two circuit for outputting a divided master timing signal whose period is twice the master period; b) a second, fixed-frequency, pulse width modulated power supply including (i) a second power switch, and (ii) circuit second means for controlling on-time, and thus duty cycle, of said second power switch so as to maintain voltage regulation of the output of said second power supply, the maximum allowable duty cycle of said second switch being 50 percent, said circuit second means including (I) a slave clock means for outputting a slave timing signal having a slave period and (II) a slave divide-by-two circuit for outputting a divided slave timing signal whose period is twice the slave period; c) circuit third means, connected to the master clock means and the master and slave divide-by-two circuits, for causing synchronization pulses, of a period equal to the master period, to be delivered to the slave clock means such that the slave period becomes equal to the master period, and for causing the slave divide-by-two circuit to be reset so that the divided master and divided slave timing signals are 180° out of phase, and so that the beginning of the first power switch on-time is 180° out of phase with the beginning of the second power switch on-time; and d) circuit fourth means, connected to said first and second supplies, and to said third means, for automatically disabling, when an undervoltage condition is detected on the output of either the first or second supplies, (i) the synchronization pulses to the slave clock means and (ii) the resetting of the slave divide-by-two circuit; e) the on-times of said first and second switches being capable of being different from one another during synchronization; the circuit third and fourth means comprising: first and second AND gates; first and second inverters; first and second undervoltage detectors; a logic OR circuit comprising two suitably interconnected transistors; and a diode; said first AND gate connected to the outputs of the master divide-by-two circuit and the slave divide-by-two circuit; said first inverter connected to the output of the master clock means; said diode connected to the output of the first inverter; said second inverter connected to the output of the diode; said second AND gate connected to the outputs of the first AND gate and the second inverter; said second AND gate having output connected to reset the slave divide-by-two circuit; the diode having output connected for effecting said synchronization pulses; said first and second undervoltage detectors having inputs connected to the outputs of said first and second supplies, respectively; said logic OR circuit connected to the outputs of the first and second undervoltage detectors and for outputting, to the junction of the diode and the second inverter, whenever either or both of the first and second undervoltage detectors detects a low voltage condition on its input, a signal preventing both the synchronization of the clocks and the resetting of the slave divide-by-two circuit.

Claim 16

The method as defined in claim 11 and including reinstating the synchronization when both DC outputs are no longer overloaded.

Claim 17

Apparatus comprising: first and second pulse width modulated power supplies having, respectively, (i) first and second clocks, (ii) first and second power switches each capable of on and off states, and (iii) first and second DC outputs; and circuit means for (a) synchronizing the first and second clocks such that turn-on transitions of said first power switch are at the same frequency as, but phase shifted 180° relative to, turn-on transitions of the second power switch, the duration of the on state of the first power switch being capable, during synchronization, of being unequal to the duration of the on state of the second power switch, and the on states of the first and second power switches being prevented from any overlapping of one another during synchronization, and (b) automatically disabling the synchronization when at least one of the first and the second DC outputs is overloaded.

Claim 18

Apparatus comprising: first and second pulse width modulated power supplies having, respectively, (i) first and second clocks, (ii) first and second power switches each capable of on and off states, and (iii) first and second DC outputs; and circuit means for (a) synchronizing the first and second clocks such that turn-on transitions of said first power switch are at the same frequency as, but phase shifted 180° relative to, turn-on transitions of the second power switch, the duration of the on state of the first power switch being capable, during synchronization, of being unequal to the duration of the on state of the second power switch, and the on states of the first and second power switches being prevented from any overlapping of one another during synchronization, and (b) automatically disabling the synchronization when at least one of the first and the second DC outputs is overloaded.

Claim 19

Apparatus as defined in claim 13 wherein said circuit means automatically reinstates the synchronization when both DC outputs are no longer overloaded.