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US5129073A
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Dynamic RAM with read-write/refresh mode judging capability
Assignee: Sharp Corp
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Filing: 1991-09-12
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Granted: 1992-07-07
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Expires: 2011-09-12
Abstract
Abstract A dynamic random-access memory contains within itself a logical circuit which judges from an address signal received from an external system whether this external system is accessing the memory or not and, if the external system is found to be accessing it, the address specified by this address signal is selected but, if the external system is found not to be accessing it, an address outputted from an internally contained address counter is selected for refresh.
Inventors
- 👤 Yukichi Murakami
- 👤 Keiichi Miyata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:51
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
133 words
A dynamic random-access memory comprising a logical circuit which receives from an external system an address signal with a plural N-number of binary digits, examines only an n-number of specified digits out of said N binary digits of said received address signal where n is smaller than N and makes a determination only from said n specified digits of said received address signal whether or not said external system is accessing said memory, an address counter for refresh, and means for selecting on the basis of said determination by said logical circuit either an address from said external system if said logical circuit determines that said external system is accessing said memory or an address from said address counter if said logical circuit determines that said external system is not accessing said memory.
Claim 2
Dependent Claim
133 words
A dynamic random-access memory comprising a logical circuit which receives from an external system an address signal with a plural N-number of binary digits, examines only an n-number of specified digits out of said N binary digits of said received address signal where n is smaller than N and makes a determination only from said n specified digits of said received address signal whether or not said external system is accessing said memory, an address counter for refresh, and means for selecting on the basis of said determination by said logical circuit either an address from said external system if said logical circuit determines that said external system is accessing said memory or an address from said address counter if said logical circuit determines that said external system is not accessing said memory.
Claim 3
Dependent Claim
49 words
The memory of claim 1 further comprising a memory cell array, a row address decoder for selecting a row address in said array, and a column address decoder for selecting a column address in said array, said selecting means being a multiplexer for providing address signals by time division.
Claim 4
Dependent Claim
24 words
The memory of claim 1 wherein said logical circuit, said address counter and said selecting means are contained in said memory as parts thereof.
Claim 5
Dependent Claim
18 words
The memory of claim 1 wherein said specified digits are the highest n digits of said N digits.
Claim 6
Dependent Claim
12 words
The memory of claim 1 wherein said binary digits represent an address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |