US5128674A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two quadrants high speed multiplying DAC
Assignee: Microelectronics Technology Inc
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Filing: 1991-03-28
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Granted: 1992-07-07
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Expires: 2011-03-28
Abstract
Abstract A multiplying digital-to-analog converter for multiplying a bipolar input current by a digital word A having N bits a i including a current adder for adding a constant current to the bipolar input current to produce a unipolar current, a first current mirror responsive to the unipolar current for providing N binary weighted versions of the unipolar current, a second current mirror for providing binary weighted versions of the constant current, N current selection circuits respectively controlled the N bits a i for providing an output current comprising (a) the correspondingly weighted version of said unipolar current if the associated control bit is in a first state or (b) the correspondingly weighted version of the constant current if the associated control bit is in a second state, and a shifting circuit for summing the outputs of said N current selection means and for shifting the sum current to produce a bipolar output current representative of product of (a) the input bipolar current and (b) the digital word A.
Inventors
- 👤 Kam W. Kong
- 👤 John M. Burns
- 👤 Tim M. Ng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:43
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/742; H03M1/745
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
177 words
A multiplying digital-to-analog converter for multiplying a bipolar input signal by a discrete gain factor K represented by a digital word A having N bits a i comprising: adding means responsive to the bipolar input signal for adding a constant signal to the bipolar signal to produce a unipolar signal; first weighting means responsive to said unipolar signal for providing N binary weighted versions of said unipolar signal; second weighting means for providing N binary weighted versions of the constant signal; N signal selection means respectively controlled by said N bits a i for providing an output signal comprising (a) said correspondingly weighted version of said unipolar signal if the associated control bit is in a first state, or (b) said correspondingly weighted version of the constant signal if the associated control bit is in a second state; and shifting means for summing the outputs of said N signal selection means and for shifting said sum to produce a bipolar output signal representative of product of (a) the bipolar input signal and (b) the digital word A.
Claim 2
Dependent Claim
177 words
A multiplying digital-to-analog converter for multiplying a bipolar input signal by a discrete gain factor K represented by a digital word A having N bits a i comprising: adding means responsive to the bipolar input signal for adding a constant signal to the bipolar signal to produce a unipolar signal; first weighting means responsive to said unipolar signal for providing N binary weighted versions of said unipolar signal; second weighting means for providing N binary weighted versions of the constant signal; N signal selection means respectively controlled by said N bits a i for providing an output signal comprising (a) said correspondingly weighted version of said unipolar signal if the associated control bit is in a first state, or (b) said correspondingly weighted version of the constant signal if the associated control bit is in a second state; and shifting means for summing the outputs of said N signal selection means and for shifting said sum to produce a bipolar output signal representative of product of (a) the bipolar input signal and (b) the digital word A.
Claim 3
Dependent Claim
36 words
The multiplying digital-to-analog converter of claim 1 wherein said shifting means subtracts the sum of said N binary weighted versions of the constant signal from the sum of said outputs of said N signal selection means.
Claim 4
Dependent Claim
179 words
A multiplying digital-to-analog converter for multiplying a bipolar input current by a discrete gain factor K represented by a digital word A having N bits a i , comprising: adding means responsive to the bipolar input current for adding a constant current to the bipolar current to produce a unipolar current; first weighting means responsive to said unipolar current for providing N binary weighted versions of said unipolar current; second weighting means for providing N binary weighted versions of the constant current; N current selection means respectively controlled by said N bits a i for providing an output current comprising (a) said correspondingly weighted version of said unipolar current if the associated control bit is in a first state, or (b) said correspondingly weighted version of the constant current if the associated control bit is in a second state; and shifting means for summing the outputs of said N current selection means and for shifting said sum to produce a bipolar output current representative of a product of (a) the bipolar input current and (b) the digital word A.
Claim 5
Dependent Claim
179 words
A multiplying digital-to-analog converter for multiplying a bipolar input current by a discrete gain factor K represented by a digital word A having N bits a i , comprising: adding means responsive to the bipolar input current for adding a constant current to the bipolar current to produce a unipolar current; first weighting means responsive to said unipolar current for providing N binary weighted versions of said unipolar current; second weighting means for providing N binary weighted versions of the constant current; N current selection means respectively controlled by said N bits a i for providing an output current comprising (a) said correspondingly weighted version of said unipolar current if the associated control bit is in a first state, or (b) said correspondingly weighted version of the constant current if the associated control bit is in a second state; and shifting means for summing the outputs of said N current selection means and for shifting said sum to produce a bipolar output current representative of a product of (a) the bipolar input current and (b) the digital word A.
Claim 6
Dependent Claim
15 words
The multiplying digital-to-analog converter of claim 3 wherein said adding means comprises a current adder.
Claim 7
Dependent Claim
43 words
The multiplying digital-to-analog converter of claim 3 wherein said shifting means comprises a current adder that adds the sum of the outputs of the N current selection means and the negative of the sum of said binary weighted versions of the constant current.
Claim 8
Dependent Claim
232 words
A multiplying digital-to-analog converter for multiplying a bipolar input current I SX by a discrete gain factor K represented by a digital word A having N bits a i , comprising: a current adder responsive to the bipolar input current for adding a constant current I D to the bipolar current to produce a unipolar current I SY ; first weighting means responsive to said unipolar current for providing N binary weighted currents I SY , (1/2) 1 I SY , (1/2) 2 I SY , . . . (1/2) N-1 I SY based on the unipolar current; second weighting means for providing N binary weighted currents I D , (1/2) 1 I D , (1/2) 2 I D , . . . (1/2) N-1 I D based on the constant current I D ; N current selection means respectively controlled by said N bits a i for providing an output current comprising (a) said correspondingly weighted version of said unipolar current if the associated control bit is in a first state, or (b) said correspondingly weighted version of the constant current if the associated control bit is in a second state; and shifting means for summing the outputs of said N current selection means and for shifting said sum to produce a bipolar output current representative of a product of (a) the bipolar input current and (b) the digital word A.
Claim 9
Dependent Claim
232 words
A multiplying digital-to-analog converter for multiplying a bipolar input current I SX by a discrete gain factor K represented by a digital word A having N bits a i , comprising: a current adder responsive to the bipolar input current for adding a constant current I D to the bipolar current to produce a unipolar current I SY ; first weighting means responsive to said unipolar current for providing N binary weighted currents I SY , (1/2) 1 I SY , (1/2) 2 I SY , . . . (1/2) N-1 I SY based on the unipolar current; second weighting means for providing N binary weighted currents I D , (1/2) 1 I D , (1/2) 2 I D , . . . (1/2) N-1 I D based on the constant current I D ; N current selection means respectively controlled by said N bits a i for providing an output current comprising (a) said correspondingly weighted version of said unipolar current if the associated control bit is in a first state, or (b) said correspondingly weighted version of the constant current if the associated control bit is in a second state; and shifting means for summing the outputs of said N current selection means and for shifting said sum to produce a bipolar output current representative of a product of (a) the bipolar input current and (b) the digital word A.
References Cited (Backward Citations)
US4563670A
Cited
US4982192A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |