US5128567A
Expired / Lapsed
US
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Output circuit of semiconductor integrated circuit with reduced power source line noise
Assignee: Toshiba Corp
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Filing: 1989-05-01
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Granted: 1992-07-07
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Expires: 2009-05-01
Abstract
Abstract An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.
Inventors
- 👤 Fuminari Tanaka
- 👤 Satoshi Nonaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:47
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/605; G; G11; G11C; G11C5/00; G11C5/14; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K17/164; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H10D84/00; H10D84/40; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
149 words
An output circuit of a semiconductor integrated circuit comprising: a plurality of output transistors connected in common to a load and having different current driving abilities for said load; and a plurality of signal delay means with outputs thereof each connected respectively to inputs of said plurality of output transistors for delaying driving signals for driving each of said output transistors by different delay time; wherein the current driving ability of at least a first one of said plurality of output transistors, which is driven by the delay signal of one of said signal delay means which has first delay time, is set to be larger than the current driving ability of at least a second one of said plurality of output transistors, which is driven by the delay signal of one of said signal delay means which has a second delay time shorter than the first delay time.
Claim 2
Dependent Claim
149 words
An output circuit of a semiconductor integrated circuit comprising: a plurality of output transistors connected in common to a load and having different current driving abilities for said load; and a plurality of signal delay means with outputs thereof each connected respectively to inputs of said plurality of output transistors for delaying driving signals for driving each of said output transistors by different delay time; wherein the current driving ability of at least a first one of said plurality of output transistors, which is driven by the delay signal of one of said signal delay means which has first delay time, is set to be larger than the current driving ability of at least a second one of said plurality of output transistors, which is driven by the delay signal of one of said signal delay means which has a second delay time shorter than the first delay time.
Claim 3
Dependent Claim
92 words
An output of a semiconductor integrated circuit according to claim 1, wherein said plurality of output transistors are sequentially driven by the outputs of said signal delay means such that drive signals supplied to ones of said plurality of output transistors having a greater current driving ability are delayed longer than drive signals applied to ones of said plurality of output transistors having a smaller current carrying ability, thereby causing the output transistors having a greater current driving ability to be driven after the output transistors having a smaller current driving ability.
Claim 4
Dependent Claim
43 words
An output of a semiconductor integrated circuit according to claim 1, wherein each of said delay means is constituted by a time constant circuit formed of a resistor element of polysilicon and an input capacitor of a corresponding one of said output transistors.
Claim 5
Dependent Claim
142 words
A transistor circuit comprising: pre-buffer means for supplying a pre-buffer output corresponding to an input signal; first buffer means connected to said prebuffer means for supplying an output corresponding to the pre-buffer output to a preset load; second buffer means connected to said first buffer means for supplying an output corresponding to the pre-buffer output of said preset load, said second buffer means having a larger load driving ability than said first buffer means; first delay means connected in series between said pre-buffer means and said first buffer means, for delaying the pre-buffer output by a first preset delay time; and p1 second delay means connected in series between said pre-buffer means and said second buffer means, for delaying the pre-buffer output by a second preset delay time, said second preset delay time being set longer than said first preset delay time.
Claim 6
Dependent Claim
142 words
A transistor circuit comprising: pre-buffer means for supplying a pre-buffer output corresponding to an input signal; first buffer means connected to said prebuffer means for supplying an output corresponding to the pre-buffer output to a preset load; second buffer means connected to said first buffer means for supplying an output corresponding to the pre-buffer output of said preset load, said second buffer means having a larger load driving ability than said first buffer means; first delay means connected in series between said pre-buffer means and said first buffer means, for delaying the pre-buffer output by a first preset delay time; and p1 second delay means connected in series between said pre-buffer means and said second buffer means, for delaying the pre-buffer output by a second preset delay time, said second preset delay time being set longer than said first preset delay time.
Claim 7
Dependent Claim
36 words
A transistor circuit according to claim 4, wherein said first delay means includes a first resistor, said second delay means includes a second resistor and, said first resistor being connected in series with said second resistor.
Claim 8
Dependent Claim
18 words
A transistor circuit according to claim 4, wherein said first and second delay means constitute a parallel circuit.
Claim 9
Dependent Claim
82 words
A transistor circuit according to claim 4, wherein said first delay means includes a first resistor means for providing a first resistance, said second delay means includes a second resistor means for providing a second resistance, and a third resistor means, such that said first resistor means is electrically connected to said second resistor means and said third resistor means, said second resistor means and said second node of said third resistor means each being electrically connected to said second buffer means.
Claim 10
Dependent Claim
124 words
A transistor circuit comprising: inverter means for supplying a pre-buffer output corresponding to an inverted signal of an input signal; first buffer means connected to said inverter means for supplying an output corresponding to the pre-buffer output to a preset load; second buffer means connected to said first buffer means for supplying an output corresponding to the pre-buffer output to said preset load, said second buffer means having a larger load driving ability than said first buffer means; delay means connected between said inverter means and said second buffer means, for delaying the pre-buffer output by a preset delay time; and supply means for supplying, with a predetermined small time delay, a given signal corresponding to the input signal to said first buffer means.
Claim 11
Dependent Claim
124 words
A transistor circuit comprising: inverter means for supplying a pre-buffer output corresponding to an inverted signal of an input signal; first buffer means connected to said inverter means for supplying an output corresponding to the pre-buffer output to a preset load; second buffer means connected to said first buffer means for supplying an output corresponding to the pre-buffer output to said preset load, said second buffer means having a larger load driving ability than said first buffer means; delay means connected between said inverter means and said second buffer means, for delaying the pre-buffer output by a preset delay time; and supply means for supplying, with a predetermined small time delay, a given signal corresponding to the input signal to said first buffer means.
Claim 12
Dependent Claim
137 words
An output circuit of a semiconductor integrated circuit, comprising: a plurality of output transistors, each having an output node connected to a load of the output circuit and an input node connected to receive an input signal of the output circuit, each of said output transistors having different current driving abilities for the load, wherein the current driving ability of one of said output transistors is greater than that of another one of said output transistors; and delay means with plural outputs thereof for delaying the input signal by a plurality of delay times and for supplying signals, corresponding to the delayed input signals, connected to the respective input nodes of said output transistors, wherein the delay time of said one of the output transistors is longer than that of said another one of the output transistors.
Claim 13
Dependent Claim
137 words
An output circuit of a semiconductor integrated circuit, comprising: a plurality of output transistors, each having an output node connected to a load of the output circuit and an input node connected to receive an input signal of the output circuit, each of said output transistors having different current driving abilities for the load, wherein the current driving ability of one of said output transistors is greater than that of another one of said output transistors; and delay means with plural outputs thereof for delaying the input signal by a plurality of delay times and for supplying signals, corresponding to the delayed input signals, connected to the respective input nodes of said output transistors, wherein the delay time of said one of the output transistors is longer than that of said another one of the output transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |