Addressing system for a memory unit

Claim 2

In a computing system having a detachable memory unit for connection to a main body having a computing processor that can control various operations of the main body, the computing processor having a limited number of signal communication ports available for interconnection with a detachable memory unit, the improvement comprising: memory means, provided in the detachable memory unit, for storing data that can be addressed; a first communication line connected between one signal communicating port of the processor and an addressing port of the memory means; a second communication line connected between another signal communicating port of the processor and a data communicating port of the memory means; means for enabling the computing processor to generate an address of a plural number of bits for application to the memory unit and for dividing the generated address bits into two separate portions of bits; means for loading one portion of address bits on the first communication lien and another portion of address bits on the second communication line; means, provided in the detachable memory unit, for receiving and combining two separate portions of address bits from respectively the first and second communication lines to form a complete address for application to the memory means, and means for providing a multiplex transmission of data and address bits on the second communication line.

Claim 3

In a computing system having a detachable memory unit for connection to a main body having a computing processor that can control various operations of the main body, the computing processor having a limited number of signal communication ports available for interconnection with a detachable memory unit, the improvement comprising: memory means, provided in the detachable memory unit, for storing data that can be addressed; a first communication lien connected between a first signal communicating port of the processor and an addressing port of the memory means, the first signal communicating port being dedicated to addressing the memory means; a second communication line connected between a second signal communicating port of the processor and a data communicating port of the memory means, the second signal communicating port being originally connected to the computing system to receive only data; means for enabling the computing processor to generate an address of a plural number of bits for application to the memory unit and for dividing the generated address bits into two separate portions of bits, the first communication line having a smaller number of connectors than the number of bits of the address; means for loading one portion of address bits on the first communication lien within the capacity of its connectors and loading the remaining portion of the address bits on the second communication line; means, provided int he detachable memory unit, for receiving and combining two separate portions of address bits from respectively the first and second communication lines to form a complete address for application to the memory means, and means for providing a multiplex transmission of data and address bits only on the second communication line.

Claim 4

In a computing system having a detachable memory unit for connection to a main body having a computing processor that can control various operations of the main body, the computing processor having a limited number of signal communication ports available for interconnection with a detachable memory unit, the improvement comprising: memory means, provided in the detachable memory unit, for storing data that can be addressed; a first communication lien connected between a first signal communicating port of the processor and an addressing port of the memory means, the first signal communicating port being dedicated to addressing the memory means; a second communication line connected between a second signal communicating port of the processor and a data communicating port of the memory means, the second signal communicating port being originally connected to the computing system to receive only data; means for enabling the computing processor to generate an address of a plural number of bits for application to the memory unit and for dividing the generated address bits into two separate portions of bits, the first communication line having a smaller number of connectors than the number of bits of the address; means for loading one portion of address bits on the first communication lien within the capacity of its connectors and loading the remaining portion of the address bits on the second communication line; means, provided int he detachable memory unit, for receiving and combining two separate portions of address bits from respectively the first and second communication lines to form a complete address for application to the memory means, and means for providing a multiplex transmission of data and address bits only on the second communication line.