Time slot assigner for use in a serial communication system

Claim 2

A time slot assigner for use in a serial communication system, the time slot assigner comprising: memory means having an input for receiving encoded data, and a control output for providing a plurality of control signals, said memory means being comprised of: a memory data input latch for storing the encoded data; a memory array having an input coupled to the memory data input latch and having an output, the memory array comprising a plurality of frames of encoded data, each frame of encoded data having first, second, third, and fourth control bit fields which provide control information; a memory address means coupled to the memory array for addressing a predetermined portion of the memory array partially in response to the first control bit field; and a memory data output latch coupled to the output of the memory array for receiving and providing the control information from the first, second, third, and fourth control bit fields as the plurality of control signals at the control output; and a prescaler, a digital counter circuit, and a dedicated latch circuit, each having an input coupled to the memory means, the prescaler receiving the second control bit field and providing a scaled clock signal to the digital counter circuit, the digital counter circuit receiving the third control bit field and providing an address control signal to the memory address means, and the dedicated latch circuit receiving the fourth control bit field, the dedicated latch circuit providing time slot control signals for selecting a data channel for use in communicating the encoded data within the serial communication system.

Claim 3

The time slot assigner of the serial communication system of claim 1, wherein the system further comprises: a data multiplexor control portion coupled to the dedicated latch circuit and having a control input for receiving the time slot control signals, a clock input for receiving a communications clocking signal, and a plurality of outputs, each output providing a selectively activated output enable signal; and a plurality of data channels, each data channel having a control input to receive one of the selectively activated outputs of the data multiplexor control portion, a first data input/output coupled to a serial data conductor, and a second data input/output coupled to a bidirectional data bus.

Claim 4

The time slot assigner within the serial communication system of claim 2 wherein the second control bit field is an encoded bit for indicating that data communicated via the serial data conductor has either bit or byte resolution.

Claim 5

The time slot assigner within the serial communication system of claim 1 wherein the memory means receives the encoded data from a communications controller.

Claim 6

The time slot assigner within the serial communication system of claim 1 further comprising a data multiplexor controller coupled to the time slot control signals and a plurality of data channels wherein one of the plurality of data channels is selected by the data mulitplexor controller and data is communicated between a serial data conductor and a bidirectional data bus.

Claim 7

The time slot assigner within the serial communication system of claim 1 wherein the plurality of frames further comprises a first portion of frames of transmit data and a second portion of frames of receive data.

Claim 8

The time slot assigner within the serial communication system of claim 1 wherein the first control bit field is an encoded bit for indicating a last frame of the plurality of frames of encoded data in the memory means to be processed as a group of frames by coupling each frame of encoded data to a predetermined one of a plurality of data channels within the serial communication system.

Claim 11

The method of claim 8 further comprising the step of: receiving the encoded data from a communications controller.

Claim 12

The method of claim 9 wherein the step of using control information within the at least one control bit field further comprises: determining a resolution of the encoded data by determining whether the encoded data has either a bit resolution or a byte resolution in response to a logic state of the at least one control bit field.

Claim 13

A time slot assigner for use in a serial communication system, the time slot assigner comprising: storage means having an input for receiving encoded data, and a control output for providing a plurality of control signals, said storage means being comprised of: a data input latch for storing the encoded data; an array having an input coupled to the data input latch and having an output, the array comprising a plurality of frames of encoded data, each frame of encoded data having first, second, third, and fourth control bit fields which provide control information, the first and second control bit fields each being a single bit having a predetermined logic state; an address means coupled to the array for addressing a predetermined portion of the array partially in response to the first control bit field; and a data output latch coupled to the output of the array for receiving and providing the control information from the first, second, third, and fourth control bit fields as the plurality of control signals at the control output; and a prescaler, a digital counter circuit, and a dedicated latch circuit, each having an input coupled to the storage means, the prescaler receiving the second control bit field and providing a scaled clock signal to the digital counter circuit, the digital counter circuit receiving the third control bit field and providing an address control signal to the address means, and the dedicated latch circuit receiving the fourth control bit field, the dedicated latch circuit providing time slot control signals for selecting a data channel for use in communicating the encoded data within the serial communication system.

Claim 14

A time slot assigner for use in a serial communication system, the time slot assigner comprising: storage means having an input for receiving encoded data, and a control output for providing a plurality of control signals, said storage means being comprised of: a data input latch for storing the encoded data; an array having an input coupled to the data input latch and having an output, the array comprising a plurality of frames of encoded data, each frame of encoded data having first, second, third, and fourth control bit fields which provide control information, the first and second control bit fields each being a single bit having a predetermined logic state; an address means coupled to the array for addressing a predetermined portion of the array partially in response to the first control bit field; and a data output latch coupled to the output of the array for receiving and providing the control information from the first, second, third, and fourth control bit fields as the plurality of control signals at the control output; and a prescaler, a digital counter circuit, and a dedicated latch circuit, each having an input coupled to the storage means, the prescaler receiving the second control bit field and providing a scaled clock signal to the digital counter circuit, the digital counter circuit receiving the third control bit field and providing an address control signal to the address means, and the dedicated latch circuit receiving the fourth control bit field, the dedicated latch circuit providing time slot control signals for selecting a data channel for use in communicating the encoded data within the serial communication system.

Claim 15

The time slot assigner of the serial communication system of claim 11, wherein the system further comprises: a data multiplexor control portion coupled to the dedicated latch circuit and having a control input for receiving the time slot control signals, a clock input for receiving a communications clocking signal, and a plurality of outputs, each output providing a selectively activated output enable signal; and a plurality of data channels, each data channel having a control input to receive one of the selectively activated outputs of the data multiplexor control portion, a first data input/output coupled to a serial data conductor, and a second data input/output coupled to a bidirectional data bus.

Claim 16

A time slot assigner circuit for use in a serial communication system having a plurality of data channels, comprising: a memory array having a plurality of frames of encoded data, each frame of encoded data having at least one control bit field which provides control information, the memory array having an input for receiving and storing encoded data, and an output; first means coupled to the memory array for addressing a predetermined portion of the memory array partially in response to the at least one control bit field; a memory data output latch coupled to the output of the memory array for storing a predetermined frame of encoded data from the predetermined portion of the memory array; and second means coupled to the memory data output latch and the first means, the second means using control information within the at least one control bit field of the predetermined frame of encoded data to control the first means and to provide time slot control signals for selecting one of the plurality of data channels for use in communicating the encoded data within the serial communication system.

Claim 17

A time slot assigner circuit for use in a serial communication system having a plurality of data channels, comprising: a memory array having a plurality of frames of encoded data, each frame of encoded data having at least one control bit field which provides control information, the memory array having an input for receiving and storing encoded data, and an output; first means coupled to the memory array for addressing a predetermined portion of the memory array partially in response to the at least one control bit field; a memory data output latch coupled to the output of the memory array for storing a predetermined frame of encoded data from the predetermined portion of the memory array; and second means coupled to the memory data output latch and the first means, the second means using control information within the at least one control bit field of the predetermined frame of encoded data to control the first means and to provide time slot control signals for selecting one of the plurality of data channels for use in communicating the encoded data within the serial communication system.