US5126950A — Synchronous array logic circuitry and systems

Claim 1

Independent Claim 189 words

A circuit comprising: a source of clock signals; a first scan node, a second scan node, and a third scan node; a test node for supplying a test signal; a first transistor array for evaluating a set of signals, the first array having at least one first input node and a first output node; a second transistor array having at least one second input node and a second output node; a first storage element connected to receive the clock signals and connected to the second scan node; a second storage element connected to receive the clock signals and connected to the third scan node; first switching means connected to the test node, the first scan node, the first output node, and the first storage element for connecting one of the first scan node or the first output node to the first storage element under control of the test signal; and second switching means connected to the test node, the second scan node, the second output node, and the second storage element for connecting one of the second scan node or the second output node to the second storage element.

Claim 2

Dependent Claim 189 words

A circuit comprising: a source of clock signals; a first scan node, a second scan node, and a third scan node; a test node for supplying a test signal; a first transistor array for evaluating a set of signals, the first array having at least one first input node and a first output node; a second transistor array having at least one second input node and a second output node; a first storage element connected to receive the clock signals and connected to the second scan node; a second storage element connected to receive the clock signals and connected to the third scan node; first switching means connected to the test node, the first scan node, the first output node, and the first storage element for connecting one of the first scan node or the first output node to the first storage element under control of the test signal; and second switching means connected to the test node, the second scan node, the second output node, and the second storage element for connecting one of the second scan node or the second output node to the second storage element.

Claim 3

Dependent Claim 71 words

A circuit as recited in claim 1 wherein the first transistor array comprises: a first source and a second source of electrical potential; an array of transistors for evaluating a Boolean function; precharging means connected between the first source and the array; and evaluation means connected between the second source and the array, wherein the first source is connected to the second source when a conductive path exists through the array.

Claim 4

Dependent Claim 25 words

A circuit as recited in claim 2 wherein the source of clock signals is coupled to each of the precharging means and the evaluation means.

Claim 5

Dependent Claim 37 words

A circuit as recited in claim 2 wherein each transistor in the array has a control gate; and all transistors in the array corresponding to a same term in the Boolean function have commonly connected control gates.

Claim 6

Dependent Claim 15 words

A circuit as recited in claim 1 wherein the first storage element comprises a latch.

Claim 7

Dependent Claim 13 words

A circuit as recited in claim 1 wherein switching means comprises a multiplexer.

Claim 8

Dependent Claim 23 words

A circuit as recited in claim 1 wherein the first transistor array comprises a plurality of transistors connected to implement a Boolean function.

Claim 9

Dependent Claim 41 words

A circuit as recited in claim 7 wherein the array is further characterized by: ones of the plurality of transistors for implementing AND functions being serially connected; and ones of, the plurality of transistors for implementing OR functions being parallel connected.

Claim 10

Dependent Claim 20 words

A circuit as recited in claim 1 wherein the array comprises a plurality of transistors connected in an AND-OR matrix.

Claim 11

Dependent Claim 16 words

A circuit as recited in claim 9 wherein transistors performing an AND function are serially connected.

Claim 12

Dependent Claim 16 words

A circuit as recited in claim 9 wherein transistors performing an OR function are parallel connected.

Claim 13

Dependent Claim 38 words

A circuit as recited in claim 1 wherein the array of transistors comprise field effect transistors, each having a gate and a pair of diffused regions selectively connectable to each other by application of signals to the gate.

Claim 14

Dependent Claim 39 words

A circuit as recited in claim 12 wherein the array of transistors implements a Boolean equation having terms connected only by AND and OR operators, and wherein the array includes a transistor corresponding to each term of the equation.

Claim 15

Dependent Claim 20 words

A circuit as recited in claim 13 wherein the array of transistors corresponding to the same term are commonly connected.

Claim 16

Dependent Claim 45 words

A circuit as recited in claim 14 wherein the diffused regions of transistors corresponding to terms of the equation coupled by AND operators are serially connected and the diffused regions of transistors corresponding to terms of the equation coupled by OR operators are parallel connected.

Claim 17

Dependent Claim 186 words

A circuit comprising: a test node; a clock node; a scan input node; a scan output node; an array of transistors connected in an AND-OR matrix to perform a specific function, the transistors performing an AND function being serially connected, and the transistors performing an OR function being parallel connected; a storage element connected to the clock node and to the scan output node; and switching means connected to the test node, the scan input node, the array, and the storage element and operable under control of the test node for supplying signals from one of the scan input nodes or the array to the storage element, and wherein the array comprises, a first and a second potential source; a plurality of transistors connected between a first node and a second node to perform a Boolean function, each transistor having a control electrode; control means connected to each of the control electrodes for supplying control signals; charging means connected between the first potential source and the first node; and evaluation means connected between the second node and the second potential source for controllably connecting them together.

Claim 18

Dependent Claim 186 words

A circuit comprising: a test node; a clock node; a scan input node; a scan output node; an array of transistors connected in an AND-OR matrix to perform a specific function, the transistors performing an AND function being serially connected, and the transistors performing an OR function being parallel connected; a storage element connected to the clock node and to the scan output node; and switching means connected to the test node, the scan input node, the array, and the storage element and operable under control of the test node for supplying signals from one of the scan input nodes or the array to the storage element, and wherein the array comprises, a first and a second potential source; a plurality of transistors connected between a first node and a second node to perform a Boolean function, each transistor having a control electrode; control means connected to each of the control electrodes for supplying control signals; charging means connected between the first potential source and the first node; and evaluation means connected between the second node and the second potential source for controllably connecting them together.

Claim 19

Dependent Claim 103 words

A circuit as recited in claim 16 wherein the array of comprises: a first and a second potential source; a plurality of transistors connected between a first node and a second node to perform a Boolean function, each transistor having a control electrode; control means connected to each of the control electrodes for supplying control signals; charging means connected between the first potential source and the first node; and evaluation means connected between the second node and the second potential source for controllably connecting them together. evaluation means connected between the second node and the second potential source for controllably connecting them together.

Claim 20

Dependent Claim 25 words

A circuit as recited in claim 16 wherein charging means comprises a charging transistor having a control electrode connected to the source of clock signals.

Claim 21

Dependent Claim 24 words

A circuit as recited in claim 18 wherein the evaluation means comprises an evaluation transistor having a control electrode connected to the clock node.

Claim 22

Dependent Claim 20 words

A circuit as recited in claim 19 wherein the switching means is connected to the array at the first node.

Claim 23

Dependent Claim 22 words

A circuit as recited in claim 16 wherein the control electrodes for all transistors receiving a same control signal are commonly connected.

Claim 24

Dependent Claim 38 words

A circuit as recited in claim 16 wherein the array of transistors comprise field effect transistors, each having a gate and a pair of diffused regions selectively connectable to each other by application of signals to the gate.

Claim 25

Dependent Claim 39 words

A circuit as recited in claim 22 wherein the array of transistors implements a Boolean equation having terms connected only by AND and OR operators, and wherein the array includes a transistor corresponding to each term of the equation.

Claim 26

Dependent Claim 21 words

A circuit as recited in claim 23 wherein the gates of all transistors corresponding to the same term are commonly connected.

Claim 27

Dependent Claim 45 words

A circuit as recited in claim 24 wherein the diffused regions of transistors corresponding to terms of the equation coupled by AND operators are serially connected and the diffused regions of transistors corresponding to terms of the equation coupled by OR operators are parallel connected.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-06-30	1995-12-30	1996-06-30	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-06-30	1999-12-30	2000-06-30	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-06-30	2003-12-30	2004-06-30	$7700.00	Window Closed / Lapsed

Synchronous array logic circuitry and systems

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