US5126742A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital converter with double folding interpolation circuitry
Assignee: Fairchild Semiconductor Corp
•
Filing: 1990-11-06
•
Granted: 1992-06-30
•
Expires: 2010-11-06
Abstract
Abstract An analog to digital converter (ADC) is disclosed having a coarse converter to generate the most significant bits of the output and double folding interpolation circuitry to generate the least significant bits. Each side of the double folding circuit includes additional folding stages coupled to reference voltages above and below the full scale input range of the ADC to cancel offset errors and improve circuit linearity. The interpolation circuit includes one interpolation stage, having two multiplier networks, for each least significant bit. Each interpolation stage receives two pairs of signals from the preceding stage and outputs two pairs of signals to the next stage. One of the pairs of output signals from each interpolation stage is also sent to a latched comparator. The outputs of all of the latched comparators can be read directly as the ADC output bits without requiring a decoder.
Inventors
- 👤 Robert R. Schmidt
- 👤 Alfi Moscovici
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:24
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/20; H03M1/202; H03M1/203; H03M1/14; H03M1/141
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
216 words
An ADC circuit for converting an analog input signal which varies over an input range into a digital code having a plurality of binary output bits, comprising: folding circuitry including: means for providing a plurality of first reference voltages which span the input range; first folding means responsive to the analog input signal and said first reference voltages for generating a first folded signal and a second folded signal; and means for substantially reducing offset errors in said first and second folded signals, including: means for providing a second reference voltage being less than the lowest of said first reference voltages; second folding means coupled to said first folding means, said second folding means responsive to the analog input signal and said second reference voltage; means for providing a third reference voltage being greater than the highest of said first reference voltages; and third folding means coupled to said first folding means, said third folding means responsive to the analog input signal and said third reference voltage; interpolation circuitry coupled to said folding circuitry including: a first interpolation stage for providing a first output signal and a second output signal; and latching means responsive to said second output signal of said first interpolation stage for providing one of the binary output bits of the ADC circuit.
Claim 2
Dependent Claim
216 words
An ADC circuit for converting an analog input signal which varies over an input range into a digital code having a plurality of binary output bits, comprising: folding circuitry including: means for providing a plurality of first reference voltages which span the input range; first folding means responsive to the analog input signal and said first reference voltages for generating a first folded signal and a second folded signal; and means for substantially reducing offset errors in said first and second folded signals, including: means for providing a second reference voltage being less than the lowest of said first reference voltages; second folding means coupled to said first folding means, said second folding means responsive to the analog input signal and said second reference voltage; means for providing a third reference voltage being greater than the highest of said first reference voltages; and third folding means coupled to said first folding means, said third folding means responsive to the analog input signal and said third reference voltage; interpolation circuitry coupled to said folding circuitry including: a first interpolation stage for providing a first output signal and a second output signal; and latching means responsive to said second output signal of said first interpolation stage for providing one of the binary output bits of the ADC circuit.
Claim 3
Dependent Claim
33 words
The ADC circuit of claim 1 wherein said first folding means includes: a plurality of folding stages, each coupled to the analog input signal and a selected one of said first reference voltages.
Claim 4
Dependent Claim
17 words
The ADC circuit of claim 1 wherein: said first folded signal is defined by a sine function.
Claim 5
Dependent Claim
17 words
The ADC circuit of claim 3 wherein: said second folded signal is defined by a cosine function.
Claim 6
Dependent Claim
75 words
The ADC circuit of claim 1 wherein said first interpolation stage comprises: first multiplier means coupled to said folding circuitry for deriving said first output signal using said first and second folded signals, said first output signal being a function of sin 2Θ; and second multiplier means coupled to said folding circuitry for deriving said second output signal using said first and second folded signals, said second output signal being a function of cos 2Θ.
Claim 7
Dependent Claim
112 words
The ADC circuit of claim 1 and further including at least one additional interpolation stage coupled in series with said first interpolation stage, each of said additional interpolation stages comprising: third multiplier means for deriving a third output signal being a function of sin 2Θ; and fourth multiplier means for deriving a fourth output signal being a function of cos 2Θ; wherein said third and fourth output signals of each said additional interpolation stage are derived using said third and fourth output signals of the previous additional interpolation stage in the series; and means coupled to each of said fourth differential outputs for providing a binary output bit of the ADC circuit.
Claim 8
Dependent Claim
24 words
The ADC circuit of claim 1 wherein: said first interpolation stage includes multiplier means responsive to each of said first and second folded signals.
Claim 9
Dependent Claim
16 words
The ADC circuit of claim 7 wherein: said multiplier means includes a four quadrant multiplier network.
Claim 10
Independent Claim
121 words
An apparatus for converting an analog input signal which varies between an upper input value and a lower input value into a digital format, comprising: first means for receiving the analog input signal and for generating at least a first folded signal; means coupled to said first means for reducing offset errors in said first folded signal, comprising: means for balancing said first folded signal when said analog input signal is substantially equal to said upper input value; and means for balancing said first folded signal when said analog input signal is substantially equal to said lower input value; and multiplier means for receiving said first folded signal and for deriving an interpolated output signal by multiplying said first folded signal.
Claim 11
Independent Claim
121 words
An apparatus for converting an analog input signal which varies between an upper input value and a lower input value into a digital format, comprising: first means for receiving the analog input signal and for generating at least a first folded signal; means coupled to said first means for reducing offset errors in said first folded signal, comprising: means for balancing said first folded signal when said analog input signal is substantially equal to said upper input value; and means for balancing said first folded signal when said analog input signal is substantially equal to said lower input value; and multiplier means for receiving said first folded signal and for deriving an interpolated output signal by multiplying said first folded signal.
Claim 12
Dependent Claim
41 words
The apparatus of claim 9 wherein: said first means includes means for generating a second folded signal and in which said first folded signal is a function of sin Θ and said second folded signal is a function of cos Θ.
Claim 13
Dependent Claim
35 words
The apparatus of claim 10 wherein: said multiplier means includes means for deriving a first interpolated output signal being a function of sin 2Θand a second interpolated output signals being a function of cos 2Θ.
Claim 14
Dependent Claim
22 words
The apparatus of claim 9 wherein: said multiplier means includes a plurality of interpolation stages, each having first and second multiplier networks.
Claim 15
Dependent Claim
25 words
The apparatus of claim 9 and further including: means responsive to said multiplier means for providing a binary bit representative of the analog input signal.
Claim 16
Dependent Claim
26 words
The apparatus of claim 11 further including means, responsive to said second interpolated output signal, for providing a binary bit representative of the analog input signal.
Claim 17
Independent Claim
80 words
An apparatus for converting an analog input signal into a digital format, comprising: first means for receiving the analog input signal, comprising: a first double folding network for generating at least a first folded signal being a function of sin Θ; and a second folding network for generating a second folded signal being a function of cos Θ; and multiplier means for receiving said first folded signal and for deriving an interpolated output signal by multiplying said first folded signal.
Claim 18
Independent Claim
80 words
An apparatus for converting an analog input signal into a digital format, comprising: first means for receiving the analog input signal, comprising: a first double folding network for generating at least a first folded signal being a function of sin Θ; and a second folding network for generating a second folded signal being a function of cos Θ; and multiplier means for receiving said first folded signal and for deriving an interpolated output signal by multiplying said first folded signal.
Claim 19
Independent Claim
100 words
An apparatus for converting an analog input signal into a digital format, comprising: first means for receiving the analog input signal and for generating at least a first folded signal, said first means including means for reducing offset errors in said first folded signal due to certain values of the analog input signal; and multiplier means for receiving said first folded signal and for deriving an interpolated output signal by multiplying said first folded signal, wherein said offset errors are reduced before said first folded signal is applied to said multiplier means in order to derive said interpolated output signal.
Claim 20
Independent Claim
100 words
An apparatus for converting an analog input signal into a digital format, comprising: first means for receiving the analog input signal and for generating at least a first folded signal, said first means including means for reducing offset errors in said first folded signal due to certain values of the analog input signal; and multiplier means for receiving said first folded signal and for deriving an interpolated output signal by multiplying said first folded signal, wherein said offset errors are reduced before said first folded signal is applied to said multiplier means in order to derive said interpolated output signal.
References Cited (Backward Citations)
US4325054A
Cited
US4456904A
Cited
US4611196A
Cited
US4897656A
Cited
US4912469A
Cited
US4985701A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |