Time-division bit number conversion circuit

Claim 2

A bit number expansion system comprising: (a) a 2N bits signal input terminal where N is an integer; (b) a first memory having 2N bits cells connected to said signal input terminal; said first memory having upper and lower inputs and upper and lower outputs; (c) a second memory having 2N bits cells connected to the upper and lower outputs of the corresponding cells of said first memory, respectively; (d) a third memory having 2N bits cells, said third memory having upper and lower input bit terminals which are connected to the lower outputs and the lower inputs of said first memory, respectively; and (e) A first switch connected to the output of said second memory and to the output of said third memory for introducing expanded-bit output signals from one of N bits of said input terminal when said third memory is selected.

Claim 3

A bit number expansion system according to claim 1, wherein said first, second and third memories are formed of 2N D type flip-flops, respectively.

Claim 4

A bit number expansion system according to claim 1, wherein said first switch is controlled such that the output signals of said second memory are selected when the bit number of said input signal is 2N and the output signals of said third memory are selected when the bit number of said input signal is N.

Claim 5

A bit number reduction system comprising: (A) a first memory having a first set of N number of output terminals and a second set of N number of output terminals; (B) signal input means connected to said first memory; (C) a second memory having N bits cells, said second memory being supplied with output signals from said first set of N number of output terminals of said first memory; (D) a first switch for selecting the outputs of said second memory or the outputs of said second set of N number of output terminals of said first memory; and (E) a third memory having a first set of N number of inputs connected to said first set of N number of output terminals of said first memory and a second set of N number of inputs connected to the output terminal of said first switch, said third memory having a set of N number of output terminals for bit number reduction.

Claim 6

A bit number reduction system comprising: (A) a first memory having a first set of N number of output terminals and a second set of N number of output terminals; (B) signal input means connected to said first memory; (C) a second memory having N bits cells, said second memory being supplied with output signals from said first set of N number of output terminals of said first memory; (D) a first switch for selecting the outputs of said second memory or the outputs of said second set of N number of output terminals of said first memory; and (E) a third memory having a first set of N number of inputs connected to said first set of N number of output terminals of said first memory and a second set of N number of inputs connected to the output terminal of said first switch, said third memory having a set of N number of output terminals for bit number reduction.

Claim 7

A bit number reduction system according to claim 4, wherein said first and third memories include 2N D type flip-flops, and said second memory includes N D flip-flops.

Claim 8

A bit number conversion system comprising: (1) a 2N bits signal input terminal; (2) a first memory having 2N bits cells and having upper and lower inputs and upper and lower outputs, said upper and lower inputs being connected to said signal input terminal; (3) a second memory having 2N bits cells connected to the upper and lower outputs of the corresponding cells of said first memory, respectively; (4) a third memory having 2N bits cells and upper and lower inputs, said upper and lower input bit terminals thereof being connected to the lower outputs and the lower inputs of said first memory, respectively; (5) A first switch connected to the output of said second memory and to the output of said third memory for introducing an expanded-bit output signals from one of N bits of said input terminal when said third memory is selected; (6) a fourth memory having a first set of N number of output terminals and a second set of N number of output terminals; (7) a 2N bits signal input terminal connected to said fourth memory; (8) a fifth memory having N bits cells, said fifth memory being supplied with output signals from said first set of N number of output terminals of said fourth memory; (9) a second switch for selecting the outputs of said fifth memory or the outputs of said second set of N number of output terminals of said fourth memory; (10) a sixth memory having a first set of N number of inputs connected to said first set of N number of output terminals of said fourth memory and a second set of N number of inputs connected to the output terminal of said second switch, said sixth memory having a set of N number of output terminals for bit number reduction; and (11) a digital processing block having an input terminal adapted to be connected to the output of said first switch and having an output terminal adapted to be connected to said 2N bits signal input terminal of said fourth memory.

Claim 9

A bit number conversion system comprising: (1) a 2N bits signal input terminal; (2) a first memory having 2N bits cells and having upper and lower inputs and upper and lower outputs, said upper and lower inputs being connected to said signal input terminal; (3) a second memory having 2N bits cells connected to the upper and lower outputs of the corresponding cells of said first memory, respectively; (4) a third memory having 2N bits cells and upper and lower inputs, said upper and lower input bit terminals thereof being connected to the lower outputs and the lower inputs of said first memory, respectively; (5) A first switch connected to the output of said second memory and to the output of said third memory for introducing an expanded-bit output signals from one of N bits of said input terminal when said third memory is selected; (6) a fourth memory having a first set of N number of output terminals and a second set of N number of output terminals; (7) a 2N bits signal input terminal connected to said fourth memory; (8) a fifth memory having N bits cells, said fifth memory being supplied with output signals from said first set of N number of output terminals of said fourth memory; (9) a second switch for selecting the outputs of said fifth memory or the outputs of said second set of N number of output terminals of said fourth memory; (10) a sixth memory having a first set of N number of inputs connected to said first set of N number of output terminals of said fourth memory and a second set of N number of inputs connected to the output terminal of said second switch, said sixth memory having a set of N number of output terminals for bit number reduction; and (11) a digital processing block having an input terminal adapted to be connected to the output of said first switch and having an output terminal adapted to be connected to said 2N bits signal input terminal of said fourth memory.

Claim 10

A bit number conversion system according to claim 6, wherein said first, second, third, fourth, fifth and sixth memories are formed of D type flip-flop memories, respectively.

Claim 11

A bit number conversion system according to claim 6, wherein said 2N bit input signal is a chroma signal of a color television receiver.