Patent US5126602A successfully refreshed from Google Patents.
US5126602A
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US
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Digital phase detector in an NRZ bit synchronous system
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1991-06-25
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Granted: 1992-06-30
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Expires: 2011-06-25
Abstract
Abstract The object of the present invention is to provide a phase detector comprising three D-type flip-flops, which compares the transition phase of retiming clock pulses with the phase of the center of the unit bit interval of received data, produces the compared result in digital fashion to operate irrespective of the data bit speed and in the form of a phase information that is compatible with a digital circuit.
Inventors
- 👤 Bhum C. Lee
- 👤 Kwon C. Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:47
CPC Classifications
H; H03; H03L; H03L7/00; H03K; H03K5/00; H03K5/22; H03K5/26
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
382 words
A digital phase detector in an NRZ bit synchronous system including a source of NRZ data and a clock for generating clock pulses, said detector producing a logic signal indicative of a phase discrepancy between a phase of the center of an input NRZ data unit bit interval and a transition phase of an input clock pulse having a period equal to the unit bit interval of the NRZ data, said detector comprising: pulse means for producing non-inverted phase clock pulses and inverted phase clock pulses from the input clock pulses received from the clock; a first D-type flip-flop having a first D input, a first clock input and a first logic output, said first D input being coupled to said NRZ data source to receive said input NRZ data and said first clock input being coupled to said pulse means to receive said non-inverted phase clock pulses; a second D-type flip-flop having a second D input, a second clock input and a second logic output, said second D input being coupled to said NRZ data source to receive said input NRZ data and said second clock input being coupled to said pulse means to receive said inverted phase clock pulses; a third D-type flip-flop having a third D input, a third clock input and a third logic output, said third D input being coupled to said first logic output and said third clock input being coupled to said pulse means to receive said inverted phase clock pulses; a combination exclusive OR/NOR gate, for outputting a logic signal indicative of the phase discrepancy between a phase of the center of the input NRZ data unit bit interval and the transition phase of the input clock pulse, having a first input, a second input, a logic output and a logic complementary output, said first input being coupled to said third logic output and said second input being coupled to said second logic output; and an exclusive NOR gate, for outputting a logic signal indicative of a phase discrepancy between said first and said second logic outputs, having a first XNOR input, a second XNOR input, and an XNOR logic output, said first XNOR input being coupled to said first logic output and said second XNOR input being coupled to said second logic output.
Claim 2
Dependent Claim
382 words
A digital phase detector in an NRZ bit synchronous system including a source of NRZ data and a clock for generating clock pulses, said detector producing a logic signal indicative of a phase discrepancy between a phase of the center of an input NRZ data unit bit interval and a transition phase of an input clock pulse having a period equal to the unit bit interval of the NRZ data, said detector comprising: pulse means for producing non-inverted phase clock pulses and inverted phase clock pulses from the input clock pulses received from the clock; a first D-type flip-flop having a first D input, a first clock input and a first logic output, said first D input being coupled to said NRZ data source to receive said input NRZ data and said first clock input being coupled to said pulse means to receive said non-inverted phase clock pulses; a second D-type flip-flop having a second D input, a second clock input and a second logic output, said second D input being coupled to said NRZ data source to receive said input NRZ data and said second clock input being coupled to said pulse means to receive said inverted phase clock pulses; a third D-type flip-flop having a third D input, a third clock input and a third logic output, said third D input being coupled to said first logic output and said third clock input being coupled to said pulse means to receive said inverted phase clock pulses; a combination exclusive OR/NOR gate, for outputting a logic signal indicative of the phase discrepancy between a phase of the center of the input NRZ data unit bit interval and the transition phase of the input clock pulse, having a first input, a second input, a logic output and a logic complementary output, said first input being coupled to said third logic output and said second input being coupled to said second logic output; and an exclusive NOR gate, for outputting a logic signal indicative of a phase discrepancy between said first and said second logic outputs, having a first XNOR input, a second XNOR input, and an XNOR logic output, said first XNOR input being coupled to said first logic output and said second XNOR input being coupled to said second logic output.
Claim 3
Dependent Claim
382 words
A digital phase detector in an NRZ bit synchronous system including a source of NRZ data and a clock for generating clock pulses, said detector producing a logic signal indicative of a phase discrepancy between a phase of the center of an input NRZ data unit bit interval and a transition phase of an input clock pulse having a period equal to the unit bit interval of the NRZ data, said detector comprising: pulse means for producing non-inverted phase clock pulses and inverted phase clock pulses from the input clock pulses received from the clock; a first D-type flip-flop having a first D input, a first clock input and a first logic output, said first D input being coupled to said NRZ data source to receive said input NRZ data and said first clock input being coupled to said pulse means to receive said non-inverted phase clock pulses; a second D-type flip-flop having a second D input, a second clock input and a second logic output, said second D input being coupled to said NRZ data source to receive said input NRZ data and said second clock input being coupled to said pulse means to receive said inverted phase clock pulses; a third D-type flip-flop having a third D input, a third clock input and a third logic output, said third D input being coupled to said first logic output and said third clock input being coupled to said pulse means to receive said inverted phase clock pulses; a combination exclusive OR/NOR gate, for outputting a logic signal indicative of the phase discrepancy between a phase of the center of the input NRZ data unit bit interval and the transition phase of the input clock pulse, having a first input, a second input, a logic output and a logic complementary output, said first input being coupled to said third logic output and said second input being coupled to said second logic output; and an exclusive OR gate for outputting a logic signal indicative of a phase discrepancy between said first and said third logic outputs, having a first XOR input, a second XOR input, and an XOR logic output, said first XOR input being coupled to said third logic output and said second XOR input being coupled to said first logic output.
Claim 4
Dependent Claim
382 words
A digital phase detector in an NRZ bit synchronous system including a source of NRZ data and a clock for generating clock pulses, said detector producing a logic signal indicative of a phase discrepancy between a phase of the center of an input NRZ data unit bit interval and a transition phase of an input clock pulse having a period equal to the unit bit interval of the NRZ data, said detector comprising: pulse means for producing non-inverted phase clock pulses and inverted phase clock pulses from the input clock pulses received from the clock; a first D-type flip-flop having a first D input, a first clock input and a first logic output, said first D input being coupled to said NRZ data source to receive said input NRZ data and said first clock input being coupled to said pulse means to receive said non-inverted phase clock pulses; a second D-type flip-flop having a second D input, a second clock input and a second logic output, said second D input being coupled to said NRZ data source to receive said input NRZ data and said second clock input being coupled to said pulse means to receive said inverted phase clock pulses; a third D-type flip-flop having a third D input, a third clock input and a third logic output, said third D input being coupled to said first logic output and said third clock input being coupled to said pulse means to receive said inverted phase clock pulses; a combination exclusive OR/NOR gate, for outputting a logic signal indicative of the phase discrepancy between a phase of the center of the input NRZ data unit bit interval and the transition phase of the input clock pulse, having a first input, a second input, a logic output and a logic complementary output, said first input being coupled to said third logic output and said second input being coupled to said second logic output; and an exclusive OR gate for outputting a logic signal indicative of a phase discrepancy between said first and said third logic outputs, having a first XOR input, a second XOR input, and an XOR logic output, said first XOR input being coupled to said third logic output and said second XOR input being coupled to said first logic output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-06-30 | 1995-12-30 | 1996-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-30 | 1999-12-30 | 2000-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-30 | 2003-12-30 | 2004-06-30 | $7700.00 | Window Closed / Lapsed |