US5125079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for controlling the data transmission of a central unit interfacing control circuit and circuit arrangement for the implementation of the method
Assignee: Fujitsu Technology Solutions GmbH
•
Filing: 1989-09-20
•
Granted: 1992-06-23
•
Expires: 2009-09-20
Abstract
Abstract A method for controlling the data transmission of a central unit interfacing control circuit and a circuit arrangement for the implementation of the method. The control of the data transmission between a central unit and a communication controller with the central unit interfacing control circuit is guaranteed under real-time conditions on a part of the central unit channel interface and is guaranteed on a part of the communication controller with a processing speed inherent in the microprocessor unit that controls the central unit interfacing control circuit. The central unit interfacing control circuit has a ROM interface controller that controls all control executions at the central unit channel interface under real-time conditions thereby relieving the microprocessor unit. The microprocessor unit can thereby operate the communication controller interface with its maximum possible processing speed.
Inventors
- 👤 Ruediger Max
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:32
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
232 words
A method for controlling data transmission between a central unit and a communication controller with an intervening microprocessor-controlled central unit interfacing control circuit having respective interface circuits for the communication controller and for the central unit, comprising the steps of: executing all accesses to the central unit interface circuit for interfacing with the central unit by a ROM interface controller; decoding and subsequently intermediately storing in a FIFO instruction memory unit instructions sent by the central unit by the ROM interface controller; reading out as a packet, analyzing and successively handling in order according to priorities by a microprocessor the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; after reading out and handling the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller, reading out again in packet fashion by the microprocessor any further instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; if no further instructions are present in the FIFO instruction memory unit, monitoring the arrival of new instructions in the FIFO instruction memory unit, by continuous interrogation of the FIFO instruction memory unit by the microprocessor unit; and intermediately storing control instructions in a control register connected between the ROM interface controller and the microprocessor unit that controls the central unit interfacing control circuit, the control instructions being sent by the microprocessor unit.
Claim 2
Independent Claim
232 words
A method for controlling data transmission between a central unit and a communication controller with an intervening microprocessor-controlled central unit interfacing control circuit having respective interface circuits for the communication controller and for the central unit, comprising the steps of: executing all accesses to the central unit interface circuit for interfacing with the central unit by a ROM interface controller; decoding and subsequently intermediately storing in a FIFO instruction memory unit instructions sent by the central unit by the ROM interface controller; reading out as a packet, analyzing and successively handling in order according to priorities by a microprocessor the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; after reading out and handling the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller, reading out again in packet fashion by the microprocessor any further instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; if no further instructions are present in the FIFO instruction memory unit, monitoring the arrival of new instructions in the FIFO instruction memory unit, by continuous interrogation of the FIFO instruction memory unit by the microprocessor unit; and intermediately storing control instructions in a control register connected between the ROM interface controller and the microprocessor unit that controls the central unit interfacing control circuit, the control instructions being sent by the microprocessor unit.
Claim 3
Dependent Claim
29 words
The method according to claim 1, wherein the data transmission between the central unit (ZE) and the ROM interface controller (ROM-STW) is carried out in a multi-byte burst mode.
Claim 4
Dependent Claim
192 words
A microprocessor-controlled central unit interfacing control circuit functioning as a connecting element between a communication controller and a central unit, and having respective interface circuits for the communication controller and for the central unit, comprising: a ROM interface controller and a microprocessor that controls the central unit interfacing control unit, a FIFO instruction memory unit and a control register unit connected between the ROM interface controller and the microprocessor unit that controls the central unit interfacing control circuit and a central unit interface circuit for interfacing with the central unit, the central unit interface circuit being connected to the ROM interface controller via central unit command lines, the ROM interface controller being connected to the central unit interface circuit via controller control lines and being connected to the FIFO instruction memory unit via command lines, the FIFO instruction memory unit being connected to the microprocessor unit via memory command lines, the microprocessor unit being connected to the control register unit via processor message lines and the control register unit being connected via first and second processor answer back lines to the ROM interface controller and to the central unit interface circuit, respectively.
Claim 5
Dependent Claim
192 words
A microprocessor-controlled central unit interfacing control circuit functioning as a connecting element between a communication controller and a central unit, and having respective interface circuits for the communication controller and for the central unit, comprising: a ROM interface controller and a microprocessor that controls the central unit interfacing control unit, a FIFO instruction memory unit and a control register unit connected between the ROM interface controller and the microprocessor unit that controls the central unit interfacing control circuit and a central unit interface circuit for interfacing with the central unit, the central unit interface circuit being connected to the ROM interface controller via central unit command lines, the ROM interface controller being connected to the central unit interface circuit via controller control lines and being connected to the FIFO instruction memory unit via command lines, the FIFO instruction memory unit being connected to the microprocessor unit via memory command lines, the microprocessor unit being connected to the control register unit via processor message lines and the control register unit being connected via first and second processor answer back lines to the ROM interface controller and to the central unit interface circuit, respectively.
Claim 6
Dependent Claim
33 words
The microprocessor-controlled central unit interfacing control circuit (ZAS) according to claim 3, further comprising a communication controller interface circuit (DUEP-SST) for interfacing with the communication controller and connected to the microprocessor unit (MP).
Claim 7
Independent Claim
265 words
A method for controlling data transmission between a central unit and a communication controller with an intervening microprocessor-controlled central unit interfacing control circuit having respective interface circuits for the communication controller and for the central unit, comprising the steps of: executing by means of a ROM interface controller all accesses to the interface circuit for the central unit; decoding in the ROM interface controller instructions sent by the central unit to the ROM interface controller and subsequently intermediately storing in a FIFO instruction memory unit the instructions sent by the central unit; reading out as a packet, analyzing and successively handling in order according to priorities by means of a microprocessor the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; after reading out and handling the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller, reading out again in packet fashion by means of the micrporocessor any further instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; if no further instructions are present in the FIFO instruction memory unit, monitoring the arrival of new instructions in the FIFO instruction memory unit, by continuous interrogation of the FIFO instruction memory unit by the microprocessor unit; and intermediately storing control instructions in a control register connected between the ROM interface controller and the microprocessor unit that controls the central unit interfacing control circuit, the control instructions being sent by the microprocessor unit; data transmission between the central unit and the ROM interface controller being carried out in a multi-byte burst mode.
Claim 8
Independent Claim
265 words
A method for controlling data transmission between a central unit and a communication controller with an intervening microprocessor-controlled central unit interfacing control circuit having respective interface circuits for the communication controller and for the central unit, comprising the steps of: executing by means of a ROM interface controller all accesses to the interface circuit for the central unit; decoding in the ROM interface controller instructions sent by the central unit to the ROM interface controller and subsequently intermediately storing in a FIFO instruction memory unit the instructions sent by the central unit; reading out as a packet, analyzing and successively handling in order according to priorities by means of a microprocessor the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; after reading out and handling the instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller, reading out again in packet fashion by means of the micrporocessor any further instructions intermediately stored in the FIFO instruction memory unit by the ROM interface controller; if no further instructions are present in the FIFO instruction memory unit, monitoring the arrival of new instructions in the FIFO instruction memory unit, by continuous interrogation of the FIFO instruction memory unit by the microprocessor unit; and intermediately storing control instructions in a control register connected between the ROM interface controller and the microprocessor unit that controls the central unit interfacing control circuit, the control instructions being sent by the microprocessor unit; data transmission between the central unit and the ROM interface controller being carried out in a multi-byte burst mode.
References Cited (Backward Citations)
FR2070355A5
Cited
EP0045438A1
Cited
US4433378A
Cited
WO1986005293A1
Cited
EP0260693A2
Cited
US4945473A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-23 | 1995-12-23 | 1996-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-23 | 1999-12-23 | 2000-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-23 | 2003-12-23 | 2004-06-23 | $7700.00 | Window Closed / Lapsed |