EP0260693A2
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EP
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Program mode access control system
Assignee: Fujitsu Ltd
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Filing: 1987-09-17
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Granted: —
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Expires: 2007-09-17
Abstract
Abstract A group of control registers (18a) for controlling a plurality of input output devices (15-0, 15-1 ... 15-N) respectively are formed on a random access memory (18) connected to a microprocessor bus (25) of an input output control device (14), a history of a program mode access from a central processing apparatus to the RAM is recorded in a first-in first-out memory (FIFO) (19), the microprocessor (17) of the input output control device (14) reads an access information of the FIFO, accesses the group of the control registers (18a) on the RAM (18), and controls the input output device (14) according to the read control information, and thus control of a plurality of input output devices (15-0, 15-1 ... 15-N) is carried out by one input output device (14).
Inventors
- 👤 Hiroki Dai-5 Yoshimura Haitsu 201 Masuda
- 👤 Tetsuo Kawamata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 03:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/126
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
225 words
In a processing system in which a master device (12), such as a central processing unit (23) or a channel unit (26) and an input output control device (14) which carries out an interface control with each kind of input output device (15-0, 15-1 .. 15-N) under the control of said master device (12) are connected via a common bus (13), a program mode access control system comprising: an internal processor bus (25) of said input output control device (14) being connected, together with a microprocessor (17), by a group of control registers (18a) corresponding to a plurality of said input output devices (15-0, 15-1 ... 15-N), in a random access memory (18) which can be directly accessed from said master device (12); a first-in first-out memory (FIFO)(19, 29) being connected between said common bus (13) and said internal processor processor bus (25); a history of a program mode access from said master device (12) to said group of said control registers (18a) being recorded in said first-in first-out memory (19, 29); access information recorded in said first-in first-out memory (19, 29) being read by said microprocessor (17), the content of said control registers (18a) being read out in accordance with said access information so that a specified input output device among a plurality of said input output devices (15-0, 15-1 ... 15-N) is controlled.
Claim 2
Dependent Claim
225 words
In a processing system in which a master device (12), such as a central processing unit (23) or a channel unit (26) and an input output control device (14) which carries out an interface control with each kind of input output device (15-0, 15-1 .. 15-N) under the control of said master device (12) are connected via a common bus (13), a program mode access control system comprising: an internal processor bus (25) of said input output control device (14) being connected, together with a microprocessor (17), by a group of control registers (18a) corresponding to a plurality of said input output devices (15-0, 15-1 ... 15-N), in a random access memory (18) which can be directly accessed from said master device (12); a first-in first-out memory (FIFO)(19, 29) being connected between said common bus (13) and said internal processor processor bus (25); a history of a program mode access from said master device (12) to said group of said control registers (18a) being recorded in said first-in first-out memory (19, 29); access information recorded in said first-in first-out memory (19, 29) being read by said microprocessor (17), the content of said control registers (18a) being read out in accordance with said access information so that a specified input output device among a plurality of said input output devices (15-0, 15-1 ... 15-N) is controlled.
Claim 3
Dependent Claim
77 words
A program mode access control system according to claim 1, wherein each of said control registers (18a) is formed by a device status register DSR, a byte count register BCR, a memory address register MAR, and a command register CMR, and each of said input output devices (15-0, 15-1 15-N) is connected to a corresponding control register (18a) via an input output device (15-0, 15-1 ... 15-N) interface circuit provided in said input output control device (14).
Claim 4
Dependent Claim
101 words
A program mode access control system according to claim 1, wherein said FIFO (19, 29) provides a display bit region for displaying whether or not a parity error exists, a region of read/write bits for showing whether the data is read from said input output device (15-0, 15-1 ... 15-N) or the data is written and an address information on said random access memory (18), so that a number of recording times is determined in accordance with the difference between a velocity for accessing from a host device to said control register (18a) and a processing velocity of said microprocessor (17).
References Cited (Backward Citations)
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