US5123099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hot standby memory copy system
Assignee: Fujitsu Ltd
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Filing: 1988-07-15
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Granted: 1992-06-16
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Expires: 2008-07-15
Abstract
Abstract Disclosed is an electronic exchange with a hot standby memory copy system including main storage devices that are duplexed wherein to improve the processing capacity of a central processing unit and make the best use of the speed of a cache memory, in an information processing apparatus provided with central processing units, main storage devices and cache memories all of which are duplexed, first-in first-out memories that are duplexed and connected to the central processing units, a unit for simultaneously writing data, when the central processing unit writes the data into the cache memory, into the first-in first-out memory, and a unit for writing, independently of an operation of the central processing unit, the contents of a currently used one of the first-in first-out memories into a standby one of the main storage devices are provided.
Inventors
- 👤 Yuji Shibata
- 👤 Tetsuo Urushihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1666; G06F11/1658; G06F11/20; G06F11/202; G06F12/00; G06F5/00; G06F5/06
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
125 words
An information processing system, comprising: active and standby central processing units; active and standby main storage devices; active and standby cache memories connected respectively to the active and standby central processing units and to the active and standby main storage devices; and a hot standby memory copy system comprising: active and standby first-in first-out memories, corresponding to the active and standby central processing units and connected respectively to the central processing units; means for writing data, when data is written from the active central processing units into the active cache memory, simultaneously into the active first-in first-out memory; and means for writing, independently of the operation of the active central processing unit, contents of the active first-in first-out memory into the standby main storage device.
Claim 2
Dependent Claim
125 words
An information processing system, comprising: active and standby central processing units; active and standby main storage devices; active and standby cache memories connected respectively to the active and standby central processing units and to the active and standby main storage devices; and a hot standby memory copy system comprising: active and standby first-in first-out memories, corresponding to the active and standby central processing units and connected respectively to the central processing units; means for writing data, when data is written from the active central processing units into the active cache memory, simultaneously into the active first-in first-out memory; and means for writing, independently of the operation of the active central processing unit, contents of the active first-in first-out memory into the standby main storage device.
Claim 3
Dependent Claim
52 words
A system as claimed in claim 1, wherein said active and standby cache memories and said active and standby first-in first-out memories are cross connected to said active and standby main storage devices for duplexing data storage with respect to the main storage devices respectively to perform a copy back mode operation.
Claim 4
Dependent Claim
66 words
A system as claimed in claim 2, wherein, when the active cache memory connected to the active central processing unit is accessed by the active main storage device, data writing is carried out by said active cache memory to both of the main storage devices, while data reading by said active cache memory is carried out from only the active one of the main storage devices.
Claim 5
Dependent Claim
70 words
A system as claimed in claim 2, further comprising means for putting the active central processing unit into a queue mode when writing data from the active central processing unit into the active cache and into said active first-in first-out memory, if said active first-in first-out memory is full at the time when the active central processing unit is starting to write the data into said active first-in first-out memory.
Claim 6
Dependent Claim
70 words
A system as claimed in claim 2, further comprising; a bus connected to said first-in first-out memory and said main storage devices; and means, connected to said bus, for periodically sending a request for securing the bus connected to the main storage devices and, after securing the bus, reading out the contents of said active first-in first-out memory and writing the read data into both of the main storage devices.
Claim 7
Dependent Claim
69 words
A system as claimed in claim 2, said system further comprising means for referring to an empty indication of said active first-in first-out memory connected to the active one of the central processing units and, when the central processing units are switched from the active to the standby, the standby central processing unit is started as a new active central processing unit after confirming that the empty indication exists.
Claim 8
Dependent Claim
42 words
A system as claimed in claim 1, wherein, when data is written from the active central processing unit into the active cache memory, the same data is simultaneously written into the active main storage device to perform a write through mode operation.
Claim 9
Dependent Claim
61 words
A system as claimed in claim 7, further comprising means for putting the active central processing unit in a queue mode when writing data from the active central processing unit into the active cache memory and into said active first-in first-out memory, if said the active central processing unit is starting to write the data into said active first-in first-out memory.
Claim 10
Dependent Claim
56 words
A system as claimed in claim 7, said system further comprising means for notifying the standby central processing unit when there is no data to be transferred in one of said first-in first-out memories as a result of a transfer of the contents of said active first-in first-out memory to the standby duplexed main storage device.
Claim 11
Dependent Claim
77 words
A system as claimed in claim 7, further comprising means for detecting and indicating that a fault exists in said active first-in first-out memory, means for transferring data from the active central processing unit directly to the standby main storage device by bypassing the failed active first-in first-out memory, means for extending a memory access cycle with respect to the main storage devices and means for stopping an autonomous transferring operation of said active first-in first-out memory.
Claim 12
Independent Claim
123 words
An apparatus, comprising: an active central processing unit producing data; an active cache memory connected to said active central processing unit, and receiving and storing the data; an active main memory connected to said active cache memory; an active first-in first-out memory connected to said active central processing unit, receiving, storing and outputting the data, and said active cache memory and said active first-in first-out memory simultaneously receiving and storing the data; a standby central processing unit; a standby cache memory connected to said standby central processing unit; a standby main memory connected to said standby cache memory and said active first-in first-out memory and receiving and storing the data; and a standby first-in first-out memory connected to said standby central processing unit.
Claim 13
Independent Claim
123 words
An apparatus, comprising: an active central processing unit producing data; an active cache memory connected to said active central processing unit, and receiving and storing the data; an active main memory connected to said active cache memory; an active first-in first-out memory connected to said active central processing unit, receiving, storing and outputting the data, and said active cache memory and said active first-in first-out memory simultaneously receiving and storing the data; a standby central processing unit; a standby cache memory connected to said standby central processing unit; a standby main memory connected to said standby cache memory and said active first-in first-out memory and receiving and storing the data; and a standby first-in first-out memory connected to said standby central processing unit.
Claim 14
Independent Claim
218 words
An apparatus, comprising: an active central processing unit producing data; an active cache memory connected to said active central processing unit, receiving and storing the data; an active main memory connected to said active cache memory; an active first-in first-out memory connected to said active central processing unit, receiving, storing and outputting the data; a standby central processing unit; a standby cache memory connected to said standby central processing unit; a standby main memory connected to said standby cache memory and said active first-in first-out memory and receiving and storing the data; a standby first-in first-out memory connected to said standby central processing unit; an active selector connected to said active first-in first-out memory, said active cache memory, said active main memory and said standby main memory, and selectively connecting the active first-in first-out memory to both said active and standby main memories when a cache hit occurs during writing by said active central processing unit; and a standby selector connected to said standby first-in first-out memory, said standby cache memory, said standby main memory and said active main memory, and selectively connecting the standby first-in first-out memory to both said active and standby main memories when a cache hit occurs during writing by said standby central processing unit and when said standby central processing unit is activated.
Claim 15
Independent Claim
218 words
An apparatus, comprising: an active central processing unit producing data; an active cache memory connected to said active central processing unit, receiving and storing the data; an active main memory connected to said active cache memory; an active first-in first-out memory connected to said active central processing unit, receiving, storing and outputting the data; a standby central processing unit; a standby cache memory connected to said standby central processing unit; a standby main memory connected to said standby cache memory and said active first-in first-out memory and receiving and storing the data; a standby first-in first-out memory connected to said standby central processing unit; an active selector connected to said active first-in first-out memory, said active cache memory, said active main memory and said standby main memory, and selectively connecting the active first-in first-out memory to both said active and standby main memories when a cache hit occurs during writing by said active central processing unit; and a standby selector connected to said standby first-in first-out memory, said standby cache memory, said standby main memory and said active main memory, and selectively connecting the standby first-in first-out memory to both said active and standby main memories when a cache hit occurs during writing by said standby central processing unit and when said standby central processing unit is activated.
Claim 16
Independent Claim
126 words
An apparatus, comprising: an active central processing unit producing data; an active cache memory connected to said active central processing unit and receiving and storing the data; an active main memory connected to said active cache memory; an active first-in first-out memory connected to said active cache memory and receiving, storing and outputting the data, and said active cache memory and said active first-in first-out memory simultaneously receiving and storing the data; a standby central processing unit; a standby cache memory connected to said standby central processing unit; a standby main memory connected to said standby cache memory and said active first-in first-out memory, receiving and storing the data; and a standby first-in first-out memory connected to said standby cache memory and said active main memory.
Claim 17
Independent Claim
126 words
An apparatus, comprising: an active central processing unit producing data; an active cache memory connected to said active central processing unit and receiving and storing the data; an active main memory connected to said active cache memory; an active first-in first-out memory connected to said active cache memory and receiving, storing and outputting the data, and said active cache memory and said active first-in first-out memory simultaneously receiving and storing the data; a standby central processing unit; a standby cache memory connected to said standby central processing unit; a standby main memory connected to said standby cache memory and said active first-in first-out memory, receiving and storing the data; and a standby first-in first-out memory connected to said standby cache memory and said active main memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-16 | 1995-12-16 | 1996-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-16 | 1999-12-16 | 2000-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-16 | 2003-12-16 | 2004-06-16 | $7700.00 | Window Closed / Lapsed |