Data processor with addressing mode decoding function

Claim 1

In a data processor having an execution unit that processes instructions by executing a sequence of microinstructions, starting at an entry point address determined by decoding an instruction to be processed, with the processing of an instruction in the execution unit including the steps of executing an operation specified by the instruction to be processed, with an instruction to be processed including an operation code that indicates an operation to be performed and an operand specifier that specifies an addressing mode, where for a first type of instruction the entry point address is dependent on the operation code and the addressing mode specified by the operand specifier and for a second type of instruction the entry point address is dependent only on the operation code, an improved system for generating said entry point address comprising: an operation code decoder, which receives and decodes said operation code included in a given instruction to be processed, for outputting a first entry point address and for setting n enable signal when the instruction to be processed in of said first type; addressing mode detection means, which receives and decodes said operand specifier included in said given instruction to be processed, for providing detection information indicating whether the addressing mode specified by said operand specifier of said given instruction is a specific type of addressing mode; and entry point address modification means, coupled to said addressing mode detection means and said operation code decoder, for modifying said first entry point address output from said operation code decoder to form a modified entry point address when said specific type of addressing mode is indicated and said enable signal is set so that the microcode routine entry point address for processing the given instruction is modified according to whether said specific type of addressing mode is indicated by said given instruction.