Patent US5120675A successfully refreshed from Google Patents.
US5120675A
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US
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Method for forming a trench within a semiconductor layer of material
Assignee: Texas Instruments Inc
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Filing: 1990-06-01
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Granted: 1992-06-09
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Expires: 2010-06-01
Abstract
Abstract A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly therefrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semicondcutor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).
Inventors
- 👤 Gordon P. Pollack
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:01
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/693; H10P50/694; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W10/011; H10W10/012; H10W10/014; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
183 words
A method of forming a trench within a semiconductor layer of material, comprising: forming a first mask structure adjacent the semiconductor layer and having a sidewall; forming a sidewall spacer from first and second spacer layers adjacent the sidewall of the first mask structure, the first spacer layer comprising a first portion along the sidewall and a foot portion extending adjacent the semiconductor layer and said second spacer layer covering said first spacer layer; removing the portion of said sidewall spacer formed from said second spacer layer; forming a second mask structure adjacent the semiconductor layer, adjacent the sidewall spacer and opposite from the first mask structure sidewall; selectively removing only the foot portion of the first spacer layer so as to leave in place said first portion, such that a portion of the semiconductor layer between the remaining first portion and said second masked structure is exposed; and etching the exposed portion of said semiconductor layer, other portions of said semiconductor layer being protected by the first mask structure, the first portion of the first spacer layer and the second mask structure.
Claim 2
Independent Claim
183 words
A method of forming a trench within a semiconductor layer of material, comprising: forming a first mask structure adjacent the semiconductor layer and having a sidewall; forming a sidewall spacer from first and second spacer layers adjacent the sidewall of the first mask structure, the first spacer layer comprising a first portion along the sidewall and a foot portion extending adjacent the semiconductor layer and said second spacer layer covering said first spacer layer; removing the portion of said sidewall spacer formed from said second spacer layer; forming a second mask structure adjacent the semiconductor layer, adjacent the sidewall spacer and opposite from the first mask structure sidewall; selectively removing only the foot portion of the first spacer layer so as to leave in place said first portion, such that a portion of the semiconductor layer between the remaining first portion and said second masked structure is exposed; and etching the exposed portion of said semiconductor layer, other portions of said semiconductor layer being protected by the first mask structure, the first portion of the first spacer layer and the second mask structure.
Claim 3
Dependent Claim
34 words
The method of claim 1 wherein said step of forming a first spacer layer comprises forming a nitride layer, and wherein said step of forming a second spacer layer comprises forming a TEOS layer.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said step of etching said first and second spacer layers comprises anisotropic plasma etching.
Claim 5
Dependent Claim
15 words
The method of claim 1 wherein the semiconductor layer comprises a semiconductor over insulator layer.
Claim 6
Dependent Claim
65 words
The method of claim 1 wherein said step of forming a first mask structure comprises: forming a first insulating layer adjacent the semiconductor layer; forming a second insulating layer adjacent the first insulating layer and opposite the semiconductor layer; forming a third insulating layer adjacent the second insulating layer and opposite the first insulating layer; and selectively etching the first, second and third insulating layers.
Claim 7
Dependent Claim
48 words
The method of claim 5 wherein said step of forming a first insulating layer comprises forming an oxide layer, wherein said step of forming a second insulating layer comprises forming a nitride layer, and wherein said step of forming a third insulating layer comprises forming a TEOS layer.
Claim 8
Dependent Claim
93 words
The method of claim 1 wherein said step of forming a sidewall spacer comprises: forming said first spacer layer adjacent the first mask structure and the semiconductor layer from an insulating material; forming said second spacer layer adjacent the first spacer layer and opposite the semiconductor layer from an insulating material; and etching the first and second spacer layers such that the first layer comprises the first portion along the sidewall of the first mask structure and the foot portion extending adjacent the semiconductor layer and the second layer covers said first layer.
Claim 9
Dependent Claim
19 words
The method of claim 1 wherein said step of forming a second mask structure comprises growing an oxide region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-09 | 1995-12-09 | 1996-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-09 | 1999-12-09 | 2000-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-09 | 2003-12-09 | 2004-06-09 | $7700.00 | Window Closed / Lapsed |