Ring reduction logic using parallel determination of ring numbers in a plurality of functional units and forced ring numbers by instruction decoding

Claim 1

A ring reduction execution unit for generating a ring number of a ring reduction process during the execution of a pipeline instruction, said ring reduction execution unit comprising: (a) process type register means for generating a secure process signal specifying a ring reduction operation; (b) memory means for storing a first operand having a first ring number portion and a first data portion; (c) ring effective register means for storing a second ring number generated by a virtual memory management unit; (d) instruction register means for storing said pipeline instruction; (e) control store means coupled to said instruction register means and responsive to said pipeline instruction for generating a plurality of firmware microinstructions for executing said pipeline instruction; (f) decode logic means responsive to a first plurality of said firmware microinstructions for generating a plurality of ring control signals; and, (g) compare logic means, coupled to said ring effective register means, said memory means, said process type register means, and said decode logic means, for concurrently responsive to said first ring number, said second ring number, said secure process signal and said plurality of ring control signals in order to generate an effective ring number, and said ring control signals being operative to force said effective ring number to a predetermined value for selected types of said pipeline instruction.