Abstract A circuit which performs a hashing (exclusive OR) function and has a high drive output for driving large capacitive loads. The invention incorporates a hashing function into an output driver, such as address driver, by incorporating a pull-down circuit into the output driver which is responsive to the respective inputs to be hashed together. A very short setup time for the inputs and a very fast evaluation of the hashing function is made possible in accordance with the invention by precharging the pull-down circuit before the inputs are received. The pull-down circuit is arranged such that a high output is outputted only when both of the input signals in a discharge path are of the same logic level. The resulting system is not limited by slow evaluation of the hashing function and thus has improved performance.
A circuit for driving an output in accordance with first and second input signals, comprising: clocking means for providing a clocking signal; means responsive to said first and second input signals for making an exclusive OR determination of said first and second input signals; means for driving the result of said exclusive OR determination to said output when said clocking signal is in a predetermined state; and an FET responsive to an output of said driving means for precharging said exclusive OR determination means in accordance with said output of said driving means before arrival of said first and second input signals when said clocking signal is in a state other than said predetermined state.
Claim 2
Dependent Claim
115 words
A circuit for driving an output in accordance with first and second input signals, comprising: clocking means for providing a clocking signal; means responsive to said first and second input signals for making an exclusive OR determination of said first and second input signals; means for driving the result of said exclusive OR determination to said output when said clocking signal is in a predetermined state; and an FET responsive to an output of said driving means for precharging said exclusive OR determination means in accordance with said output of said driving means before arrival of said first and second input signals when said clocking signal is in a state other than said predetermined state.
Claim 3
Dependent Claim
49 words
A circuit as in claim 1, wherein said exclusive OR determination means comprises a first pair of series connected FETs responsive to said first and second input signals and a second pair of series connected FETs which is responsive to the complements of said first and second input signals.