US5115408A
Expired / Lapsed
US
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High speed multiplier
Assignee: Texas Instruments Inc
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Filing: 1991-02-05
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Granted: 1992-05-19
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Expires: 2011-02-05
Abstract
Abstract A multiplying circuit (10) receives a multiplicand A and multiplies it by multiplier B. An Octal recoder (18) recodes the multiplier B into octal digits having a value from 4 to -4. A tripling generator determines the product of three times the multipicand. Partial product generators (22a-h) connected to the Octal recoder multiplex between the multiplicand A and the 3*A product, and include shifter and inverter circuitry to generate the partial products. Signed digit adders (24a-d, 26a-b and 28) add the partial products.
Inventors
- 👤 Henry M. Darley
- 👤 Jeffrey A. Niehaus
- 👤 Kevin M. Ovens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/4824
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
128 words
A circuit for multiplying a multiplicand by a multiplier, said circuit comprising: input means for receiving the multiplicand; tripling circuitry coupled to said input means for generating an intermediate product equal to three times the multiplicand; recoding circuitry receiving said multiplier and recoding the multiplier into digits of an octal representation; partial product generators coupled to said input means, said tripling circuitry, and said recoding circuitry to generate signed digit partial products equal to the digits of the octal representation of the multiplier times the multiplicand; adding circuitry coupled to said partial product generators and arrayed as a binary tree to sum the signed digit partial products; and conversion circuitry coupled to said adding circuitry to convert the sum of the partial products to a selected numeric representation.
Claim 2
Dependent Claim
128 words
A circuit for multiplying a multiplicand by a multiplier, said circuit comprising: input means for receiving the multiplicand; tripling circuitry coupled to said input means for generating an intermediate product equal to three times the multiplicand; recoding circuitry receiving said multiplier and recoding the multiplier into digits of an octal representation; partial product generators coupled to said input means, said tripling circuitry, and said recoding circuitry to generate signed digit partial products equal to the digits of the octal representation of the multiplier times the multiplicand; adding circuitry coupled to said partial product generators and arrayed as a binary tree to sum the signed digit partial products; and conversion circuitry coupled to said adding circuitry to convert the sum of the partial products to a selected numeric representation.
Claim 3
Dependent Claim
16 words
The circuit of claim 1 wherein said adding circuitry comprises a plurality of signed digit adders.
Claim 4
Dependent Claim
23 words
The circuit of claim 1 wherein the conversion circuitry converts a signed digit number output by said adding circuitry into a binary number.
Claim 5
Dependent Claim
24 words
The circuit of claim 1 wherein the conversion circuitry converts a signed digit number output by said adding circuitry into a two's complement number.
Claim 6
Dependent Claim
28 words
The circuit of claim 1 further including input conversion circuitry, coupling the input means to the partial product generators, for translating the multiplicand into a signed digit number.
Claim 7
Dependent Claim
87 words
The circuit of claim 1 wherein said partial product generators comprise: multiplexing circuitry connected to said input means, said tripling circuitry, and said recoding circuitry; shifting means connected to said multiplexing circuitry and said recoding circuitry for producing multiples of two and four of the multiplicand in response to the digits of the octal representation of the multiplier having a magnitude of two or four; and zeroing means connected to said multiplexing circuitry for outputting a zero in response to multiplier digits having a value of zero.
Claim 8
Dependent Claim
33 words
The circuit of claim 6 wherein said partial product generators include inverting circuitry connected to an output of said shifting means and said recoding circuitry to produce an inverted sign of a number.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |