Patent US5115296A successfully refreshed from Google Patents.
US5115296A
Expired / Lapsed
US
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Preferential oxidization self-aligned contact technology
Assignee: United Microelectronics Corp
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Filing: 1991-01-14
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Granted: 1992-05-19
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Expires: 2011-01-14
Abstract
Abstract A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit has a substrate doped with a first conductivity. The substrate has field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device. Opposite type conductivity ions are implanted into the doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor. Dielectric spacers are formed on the sidewalls of the dielectric/gate electrode structures. A block out mask is formed over the source/drain regions designated to have self-aligned contacts made thereto. Opposite type conductivity ions are implanted into the substrate to form heavily doped portions to complete the formation of the source/drain regions in those nondesignated self-aligned contact regions. The block out mask is removed. The structure is subjected to an oxidizing atmosphere to preferentially oxidize polysilicon gate regions and heavily doped source/drain regions (thicker silicon dioxide) is compared to the lightly doped source/drain regions (thinner silicon dioxide). Opposite type conductivity ions are implanted into the doped subtrate to form heavily doped portion and to complete the formation of the source/drain regions in those designated self-aligned contact regions. Chemical dip etching is used to remove thin oxide over the designated self-aligned contact source/drain regions while leaving the thicker oxide layer remaining over the nondesignated source/drain regions. The appropriate metallurgy is provided to the designated self-aligned regions to electrically connect MOS field effect transistors into a desired integrated circuit.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Cheng-Han Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:08
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/65; H10P14/6502; H10W20/40; Y; Y10; Y10S; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
266 words
A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit comprising: providing a silicon substrate doped with a dopant of a first conductivity; said substrate having field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device; ion implanting opposite type conductivity ions into the said doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor; forming sidewall dielectric spacers on the sidewalls of said gate dielectric/gate electrode structures; forming a block out mask over the said source/drain regions designated to have self-aligned contacts made thereto while leaving nondesignated self-aligned contacts regions outside of the block out mask; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said nondesignated self-aligned contact regions; removing the said block out mask; subjecting the structure to an oxidizing atmosphere to preferentially oxidize polysilicon gate region and heavily doped source/drain regions as compared to the lightly doped source/drain regions; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said designated self-aligned contact regions; etching to remove thin oxide over the said designated self-aligned contact source/drain regions while leaving an oxide layer remaining over the said nondesignated source/drain contact regions; and providing the appropriate metallurgy to said designated self-aligned regions to electrically connect said MOS field effect transistors into a desired said integrated circuit.
Claim 2
Independent Claim
266 words
A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit comprising: providing a silicon substrate doped with a dopant of a first conductivity; said substrate having field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device; ion implanting opposite type conductivity ions into the said doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor; forming sidewall dielectric spacers on the sidewalls of said gate dielectric/gate electrode structures; forming a block out mask over the said source/drain regions designated to have self-aligned contacts made thereto while leaving nondesignated self-aligned contacts regions outside of the block out mask; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said nondesignated self-aligned contact regions; removing the said block out mask; subjecting the structure to an oxidizing atmosphere to preferentially oxidize polysilicon gate region and heavily doped source/drain regions as compared to the lightly doped source/drain regions; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said designated self-aligned contact regions; etching to remove thin oxide over the said designated self-aligned contact source/drain regions while leaving an oxide layer remaining over the said nondesignated source/drain contact regions; and providing the appropriate metallurgy to said designated self-aligned regions to electrically connect said MOS field effect transistors into a desired said integrated circuit.
Claim 3
Dependent Claim
29 words
The method of claim 1 wherein said substrate in N type, has only P wells in said substrate, and N+ type ion implanting is done into said P wells.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein said preferentially oxidize step is done at a temperature between about 800° to 1000° C. for more than about 5 minutes.
Claim 5
Dependent Claim
31 words
The method of claim 1 wherein said preferentially oxidize step is at a temperature between about 800° and 900° C. in a wet oxygen atmosphere for more than about 10 minutes.
Claim 6
Dependent Claim
36 words
The method of claim 1 wherein said preferentially oxidize step of the exposed surfaces produces silicon oxide of at least 150 nanometers on said N+ regions and less than about 40 nanometers on said P/N- regions.
Claim 7
Dependent Claim
23 words
The method of claim 1 wherein the said integrated circuit is a read only memory and is a complementary field effect transistor technology.
Claim 8
Dependent Claim
23 words
The method of claim 1 wherein the said metallurgy is composed of polycrystalline silicon having a thickness between about 100 to 300 nanometers.
Claim 9
Dependent Claim
21 words
The method of claim 7 wherein the said polycrystalline silicon is part of a polycide structure with a refractory metal silicide.
Claim 10
Dependent Claim
23 words
The method of claim 1 wherein the said metallurgy is composed of titanium nitride having a thickness between about 50 to 200 nanometers.
Claim 11
Dependent Claim
23 words
The method of claim 1 wherein the said metallurgy is composed of titanium silicide having a thickness between about 20 to 100 nanometers.
Claim 12
Independent Claim
284 words
A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit comprising: providing a silicon substrate doped with a dopant of a first conductivity; said substrate having field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device; forming sidewall dielectric spacers on the sidewalls of said gate dielectric/gate electrode structures; forming a block out mask over the said source/drain regions designated to have self-aligned contacts made thereto while leaving nondesignated self-aligned contacts regions outside of the block out mask; ion implanting opposite type conductivity ions of both arsenic and phosphorous into the said doped substrate to form heavily doped portion of arsenic and a lightly doped portion of phosphorous to complete the formation of the source/drain regions in those said nondesignated self-aligned contact regions; removing the said block out mask; subjecting the structure to an oxidizing atmosphere to preferentially oxidize polysilicon gate region and heavily doped source/drain regions as compared to the lightly doped source/drain regions; forming a block out mask pattern to leave uncovered the said self-aligned contact designated source/drain regions; ion implanting opposite type conductivity arsenic and phosphorous ions into the said doped substrate to form arsenic heavily doped portion and phosphorous lightly doped portion to complete the formation of the source/drain regions in those said designated self-aligned contact regions; removing the said block out mask; etching to remove thin oxide over the said designated self-aligned contact source/drain regions while leaving an oxide layer remaining over the said nondesignated source/drain contact regions; and providing the appropriate metallurgy to said designated self-aligned regions to electrically connect said MOS field effect transistors into a desired said integrated circuit.
Claim 13
Independent Claim
284 words
A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit comprising: providing a silicon substrate doped with a dopant of a first conductivity; said substrate having field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device; forming sidewall dielectric spacers on the sidewalls of said gate dielectric/gate electrode structures; forming a block out mask over the said source/drain regions designated to have self-aligned contacts made thereto while leaving nondesignated self-aligned contacts regions outside of the block out mask; ion implanting opposite type conductivity ions of both arsenic and phosphorous into the said doped substrate to form heavily doped portion of arsenic and a lightly doped portion of phosphorous to complete the formation of the source/drain regions in those said nondesignated self-aligned contact regions; removing the said block out mask; subjecting the structure to an oxidizing atmosphere to preferentially oxidize polysilicon gate region and heavily doped source/drain regions as compared to the lightly doped source/drain regions; forming a block out mask pattern to leave uncovered the said self-aligned contact designated source/drain regions; ion implanting opposite type conductivity arsenic and phosphorous ions into the said doped substrate to form arsenic heavily doped portion and phosphorous lightly doped portion to complete the formation of the source/drain regions in those said designated self-aligned contact regions; removing the said block out mask; etching to remove thin oxide over the said designated self-aligned contact source/drain regions while leaving an oxide layer remaining over the said nondesignated source/drain contact regions; and providing the appropriate metallurgy to said designated self-aligned regions to electrically connect said MOS field effect transistors into a desired said integrated circuit.
Claim 14
Dependent Claim
29 words
The method of claim 11 wherein said substrate is N type, has only P wells in said substrate, and N+ type ion implanting is done into said P wells.
Claim 15
Dependent Claim
27 words
The method of claim 11 wherein said preferentially oxidize step is done at a temperature between about 800° to 1000° C. for more than about 5 minutes.
Claim 16
Dependent Claim
31 words
The method of claim 11 wherein said preferentially oxidize step is at a temperature between about 800° and 900° C. in a wet oxygen atmosphere for more than about 10 minutes.
Claim 17
Dependent Claim
36 words
The method of claim 11 wherein said preferentially oxidize step of the exposed surfaces produces silicon oxide of at least 150 nanometers on said N+ regions and less than about 40 nanometers on said P/N- regions.
Claim 18
Dependent Claim
23 words
The method of claim 11 wherein the said integrated circuit is a read only memory and is a complementary field effect transistor technology.
Claim 19
Dependent Claim
23 words
The method of claim 11 wherein the said metallurgy is composed of polycrystalline silicon having a thickness between about 100 to 300 nanometers.
Claim 20
Dependent Claim
21 words
The method of claim 17 wherein the said polycrystalline silicon is part of a polycide structure with a refractory metal silicide.
Claim 21
Dependent Claim
23 words
The method of claim 11 wherein the said metallurgy is composed of titanium nitride having a thickness between about 50 to 200 nanometers.
Claim 22
Dependent Claim
23 words
The method of claim 11 wherein the said metallurgy is composed of titanium silicide having a thickness between about 20 to 100 nanometers.
Claim 23
Dependent Claim
266 words
A self-aligned contact MOS field effect transistor integrated circuit made by the method comprising: providing a silicon substrate doped with a dopant of a first conductivity; said substrate having field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device; ion implanting opposite type conductivity ions into the said doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor; forming sidewall dielectric spacers on the sidewalls of said gate dielectric/gate electrode structures; forming a block out mask over the said source/drain regions designated to have self-aligned contacts made thereto while leaving nondesignated self-aligned contact regions outside of the block out mask; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said nondesignated self-aligned contact regions; removing the said block out mask; subjecting the structure to an oxidizing atmosphere to preferentially oxidize polysilicon gate region and heavily doped source/drain regions as compared to the lightly doped source/drain regions; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said designated self-aligned contact regions; etching to remove thin oxide over the said designated self-aligned contact source/drain regions while leaving an oxide layer remaining over the said nondesignated source/drain contact regions; and providing the appropriate metallurgy to said designated self-aligned regions to electrically connect said MOS field effect transistors into a desired said integrated circuit.
Claim 24
Dependent Claim
266 words
A self-aligned contact MOS field effect transistor integrated circuit made by the method comprising: providing a silicon substrate doped with a dopant of a first conductivity; said substrate having field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device; ion implanting opposite type conductivity ions into the said doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor; forming sidewall dielectric spacers on the sidewalls of said gate dielectric/gate electrode structures; forming a block out mask over the said source/drain regions designated to have self-aligned contacts made thereto while leaving nondesignated self-aligned contact regions outside of the block out mask; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said nondesignated self-aligned contact regions; removing the said block out mask; subjecting the structure to an oxidizing atmosphere to preferentially oxidize polysilicon gate region and heavily doped source/drain regions as compared to the lightly doped source/drain regions; ion implanting opposite type conductivity ion into the said doped substrate to form heavily doped portion and to complete the formation of the source/drain regions in those said designated self-aligned contact regions; etching to remove thin oxide over the said designated self-aligned contact source/drain regions while leaving an oxide layer remaining over the said nondesignated source/drain contact regions; and providing the appropriate metallurgy to said designated self-aligned regions to electrically connect said MOS field effect transistors into a desired said integrated circuit.
Claim 25
Dependent Claim
19 words
The integrated circuit of claim 21 wherein said silicon oxide is at least 150 nanometers on said N+ regions.
Claim 26
Dependent Claim
16 words
The integrated circuit of claim 21 wherein the said integrated circuit is a read only memory.
Claim 27
Dependent Claim
24 words
The integrated circuit of claim 21 wherein the said metallurgy is composed of polycrystalline silicon having a thickness between about 100 to 300 nanometers.
Claim 28
Dependent Claim
22 words
The integrated circuit of claim 21 wherein the said polycrystalline silicon is part of a polycide structure with a refractory metal silicide.
Claim 29
Dependent Claim
24 words
The integrated circuit of claim 21 wherein the said metallurgy is composed of titanium nitride having a thickness between about 50 to 200 nanometers.
Claim 30
Dependent Claim
24 words
The integrated circuit of claim 21 wherein the said metallurgy is composed of titanium silicide having a thickness between about 20 to 100 nanometers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-19 | 1995-11-18 | 1996-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-19 | 1999-11-18 | 2000-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-19 | 2003-11-18 | 2004-05-19 | $7700.00 | Window Closed / Lapsed |