Chopper-stabilized amplifier with spread-spectrum clocking

Claim 2

A high bandwidth chopper-stabilized amplifier (CSA), comprising: a main electrical signal amplifier, an auxiliary electrical signal amplifier connected in a chopper-stabilizer circuit with said main amplifier to reduce the input voltage offset (V OS ) of the main amplifier, and means for operating said chopper-stabilized circuit at a dynamically varying randomized chopping signal frequency that substantially reduces intermodulation distortion between the input signal to the main amplifier and the chopping signal.

Claim 3

The CSA of claim 1, said operating means comprising means for operating said chopper-stabilized circuit at a pseudo-random chopping signal frequency.

Claim 4

A high bandwidth chopper-stabilized amplifier (CSA), comprising: a main electrical signal amplifier, an auxiliary electrical signal amplifier connected in a chopper-stabilized circuit with said main amplifier to reduce the input voltage offset (V OS ) of the main amplifier, and means for operating said chopper-stabilized circuit at a pseudo-random chopping signal frequency that substantially reduces intermodulation distortion between the input signal to the main amplifier and the chopping signal, said operating means including a pseudo-random bit sequence (PRBS) generator which has two output states and repeatedly cycles through a predetermined number of output bits, said PRBS generator producing one output state one time more than the other output state during each cycle.

Claim 5

A high bandwidth chopper-stabilized amplifier (CSA), comprising: a main electrical signal amplifier, an auxiliary electrical signal amplifier connected in a chopper-stabilized circuit with said main amplifier to reduce the input voltage offset (V OS ) of the main amplifier, and means for operating said chopper-stabilized circuit at a pseudo-random chopping signal frequency that substantially reduces intermodulation distortion between the input signal to the main amplifier and the chopping signal, said operating means including a pseudo-random bit sequence (PRBS) generator which has two output states and repeatedly cycles through a predetermined number of output bits, said PRBS generator producing one output state one time more than the other output state during each cycle.

Claim 6

A high bandwidth chopper-stabilized amplifier (CSA) comprising: a main operational amplifier (op amp) having inverting, non-inverting and nulling inputs and an output, its output and inverting input connected in an amplifying feedback circuit, an auxiliary op amp having inverting, non-inverting and nulling inputs and an output, its output connected to the nulling inputs of said main and auxiliary op amps through first and second switches, respectively, a third switch connecting the inverting input of said main op amp to the inverting input of said auxiliary op amp, a fourth switch connecting the non-inverting input of said auxiliary op amp to the inverting input of said auxiliary op amp, main and auxiliary signal holding means connected to the nulling inputs for said main and auxiliary op amps, respectively, chopper signal means for producing a chopping signal having alternating states and a dynamically varying randomized frequency, and means connecting said chopper signal means with said first, second, third and fourth switches so that said first and third switches are closed and said second and fourth switches are open during one chopper signal state, and vice versa during the other chopper signal state.

Claim 7

A high bandwidth chopper-stabilized amplifier (CSA) comprising: a main operational amplifier (op amp) having inverting, non-inverting and nulling inputs and an output, its output and inverting input connected in an amplifying feedback circuit, an auxiliary op amp having inverting, non-inverting and nulling inputs and an output, its output connected to the nulling inputs of said main and auxiliary op amps through first and second switches, respectively, a third switch connecting the inverting input of said main op amp to the inverting input of said auxiliary op amp, a fourth switch connecting the non-inverting input of said auxiliary op amp to the inverting input of said auxiliary op amp, main and auxiliary signal holding means connected to the nulling inputs for said main and auxiliary op amps, respectively, chopper signal means for producing a chopping signal having alternating states and a dynamically varying randomized frequency, and means connecting said chopper signal means with said first, second, third and fourth switches so that said first and third switches are closed and said second and fourth switches are open during one chopper signal state, and vice versa during the other chopper signal state.

Claim 8

The CSA of claim 4, said chopper signal means comprising means for producing a chopping signal having a pseudo-random frequency.

Claim 9

A high bandwidth chopper-stabilized amplifier (CSA), comprising: a main operational amplifier (op amp) having inverting, non-inverting and nulling inputs and an output, its output and inverting input connected in an amplifying feedback circuit, an auxiliary op amp having inverting, non-inverting and nulling inputs and an output, its output connected to the nulling inputs of said main and auxiliary op amps through first and second switches, respectively, a third switch connecting the inverting input of said main op amp to the inverting input of said auxiliary op amp, a fourth switch connecting the non-inverting input of said auxiliary op amp to the inverting input of said auxiliary op amp, main and auxiliary signal holding means connected to the nulling inputs for said main and auxiliary op amps, respectively, chopper signal means for producing a chopping signal having alternating states and a pseudo-random frequency, said chopper signal means including a pseudo-random bit sequence (PRBS) generator which has two output states and repeatedly cycles through a predetermined number of output bits, said PRBS generator producing one output state one time more than the other output state during each cycle, and means connecting said chopper signal means with said first, second, third and fourth switches so that said first and third switches are closed and said second and fourth switches are open during one chopper signal state, and vice versa during the other chopper signal state.

Claim 10

A high bandwidth chopper-stabilized amplifier (CSA), comprising: a main operational amplifier (op amp) having inverting, non-inverting and nulling inputs and an output, its output and inverting input connected in an amplifying feedback circuit, an auxiliary op amp having inverting, non-inverting and nulling inputs and an output, its output connected to the nulling inputs of said main and auxiliary op amps through first and second switches, respectively, a third switch connecting the inverting input of said main op amp to the inverting input of said auxiliary op amp, a fourth switch connecting the non-inverting input of said auxiliary op amp to the inverting input of said auxiliary op amp, main and auxiliary signal holding means connected to the nulling inputs for said main and auxiliary op amps, respectively, chopper signal means for producing a chopping signal having alternating states and a pseudo-random frequency, said chopper signal means including a pseudo-random bit sequence (PRBS) generator which has two output states and repeatedly cycles through a predetermined number of output bits, said PRBS generator producing one output state one time more than the other output state during each cycle, and means connecting said chopper signal means with said first, second, third and fourth switches so that said first and third switches are closed and said second and fourth switches are open during one chopper signal state, and vice versa during the other chopper signal state.

Claim 13

The method of claim 7, wherein said operating step comprises operating said CSA circuit with a pseudo-random chopping frequency.

Claim 14

The method of claim 7, further comprising the steps of generating said randomized chopping frequency in response to a fixed frequency clock signal, and using said CSA circuit to amplify an input signal having a frequency substantially greater than half the clock frequency, with substantially no intermodulation distortion between said input and clock signals.