Forming planar ITO gate electrode array structures

Claim 1

A method of forming a planar ITO gate electrode array structure with sub-micron spacing between such ITO gates, comprising the steps of: a sequentially providing layers of ITO, polysilicon and LTO oxide; (b) patterning the LTO layer to form spaced LTO structures which have rectangular cross-sections and exposing the surface of the polysilicon layer between such spaced LTO structures; (c) forming a conformal thin nitride layer on the exposed polysilicon and the LTO structures; (d) forming a conformal oxide layer on the thin nitride layer; (e) anisotropically etching the oxide layer and nitride layer to expose the poly layer and the top surface of the LTO structures while leaving oxide spacers over L-shaped nitride portions between such structures; (f) removing the oxide spacers leaving L-shaped nitride portions between the LTO structures; (g) oxidizing the exposed polysilicon between the L-shaped nitride portions; (h) removing the L-shaped nitride portions providing sub-micron openings between the LTO and the oxidized polysilicon; (i) anisotropically etching a polysilicon down to the ITO layer through the sub-micron openings formed between the LTO structures and the oxidized polysilicon; (j) removing the LTO structures and the oxidized polysilicon; (k) anisotropically etching the ITO through the sub-micron openings formed between the polysilicon; and (l) removing the polysilicon layer leaving a planar ITO gate electrode array structure.

Claim 2

A method of forming a planar ITO gate electrode array structure with sub-micron spacing between such ITO gates, comprising the steps of: a sequentially providing layers of ITO, polysilicon and LTO oxide; (b) patterning the LTO layer to form spaced LTO structures which have rectangular cross-sections and exposing the surface of the polysilicon layer between such spaced LTO structures; (c) forming a conformal thin nitride layer on the exposed polysilicon and the LTO structures; (d) forming a conformal oxide layer on the thin nitride layer; (e) anisotropically etching the oxide layer and nitride layer to expose the poly layer and the top surface of the LTO structures while leaving oxide spacers over L-shaped nitride portions between such structures; (f) removing the oxide spacers leaving L-shaped nitride portions between the LTO structures; (g) oxidizing the exposed polysilicon between the L-shaped nitride portions; (h) removing the L-shaped nitride portions providing sub-micron openings between the LTO and the oxidized polysilicon; (i) anisotropically etching a polysilicon down to the ITO layer through the sub-micron openings formed between the LTO structures and the oxidized polysilicon; (j) removing the LTO structures and the oxidized polysilicon; (k) anisotropically etching the ITO through the sub-micron openings formed between the polysilicon; and (l) removing the polysilicon layer leaving a planar ITO gate electrode array structure.