Manufacturing method of well region in coms intergrated circuit

Claim 2

A manufacturing method of CMOS integrated circuit device comprising the steps of: ion-implanting first impurities into a MOS transistor area defined at a main surface portion of a semiconductor substrate, said first impurities representing a conductivity type that is equal to a conductivity type of said semiconductor substrate and said MOS transistor area having an element formation region and an isolation region; forming an oxidation-resist film to cover said element formation region of said MOS transistor area except said isolation region; performing oxidation treatment by using said oxidation-resist film as a mask to form a field oxide film embedded partially in said isolation region and to form a channel stopper under said field oxide film by said first impurities; and ion-implanting second impurities representing the same conductivity type of said first impurities into said element formation region by using said field oxide film as a mask thereby to form a well region having a predetermined impurity profile in said element formation region.

Claim 3

The manufacturing method of a CMOS integrated circuit device as claimed in claim 1, wherein said conductivity type is N type and each of said first and second impurities is phosphorus.

Claim 4

The manufacturing method of a CMOS integrated circuit device as claimed in claim 1, wherein the dose of said first impurities is smaller than the dose of the said second impurities.

Claim 5

The manufacturing method of a CMOS integrated circuit device as claimed in claim 1, wherein the dose of said first impurities is not less than 1×10 12 cm -2 .

Claim 8

The manufacturing method of a CMOS integrated circuit device as claimed in claim 5, wherein each of said first and second impurities is phosphorus.

Claim 9

The manufacturing method of a CMOS integrated circuit device as claimed in claim 5, wherein the dose of said first impurities is smaller than the dose of said second impurities.

Claim 10

The manufacturing method of a CMOS integrated circuit device as claimed in claim 5, wherein the dose of said first impurities is not less than 1×10 12 cm -2 .

Claim 11

A manufacturing method of a CMOS integrated circuit comprising: a step of forming an SiO 2 film on a main surface of an N-type silicon substrate; a step of forming a first mask on a first element formation region for forming a P-channel MOS transistor and on a first element isolation region of the P-channel MOS transistor; a step of forming first P-type ion implantation layers in a second element formation region for forming an N-channel MOS transistor and in a second element isolation region of the N-channel MOS transistor, by using said first mask; a step of forming a second mask on said second element formation region and on said second element isolation region, after removing said first mask; a step of forming first N-type ion implantation layers in said first element formation region and in said second element isolation region by using said second mask; a step of removing said second mask; a step of forming an oxidation-resist film all over the top surface; a step of forming a third mask on said first and second element formation regions; a step of etching said oxidation-resist film by using said third mask; a step of forming a fourth mask on said first element formation region and on said first element isolation region by not removing said third mask; a step of forming a second P-type ion implantation layer on said second element isolation region by using said second mask and said fourth mask; a step of removing said third mask and said fourth mask; a step of performing heat treatment to said substrate thereby to form P wells by converting said first P-type ion implantation layers thereto, to form N-type channel stopper by converting said first N-type ion implantation layers thereto, to form a P-type channel stopper by converting said second P-type ion implantation layer thereto and to form a field insulator film in said first and second element isolation regions by using said oxidation-resist film; a step of forming a fifth mask on said P wells; a step of forming a second N-type ion implantation layer in said first element formation region by using said fifth mask; a step of removing said fifth mask; and a step of performing heat treatment to form an N well by said second N-type ion implantation layer.

Claim 12

A manufacturing method of a CMOS integrated circuit comprising: a step of forming an SiO 2 film on a main surface of an N-type silicon substrate; a step of forming a first mask on a first element formation region for forming a P-channel MOS transistor and on a first element isolation region of the P-channel MOS transistor; a step of forming first P-type ion implantation layers in a second element formation region for forming an N-channel MOS transistor and in a second element isolation region of the N-channel MOS transistor, by using said first mask; a step of forming a second mask on said second element formation region and on said second element isolation region, after removing said first mask; a step of forming first N-type ion implantation layers in said first element formation region and in said second element isolation region by using said second mask; a step of removing said second mask; a step of forming an oxidation-resist film all over the top surface; a step of forming a third mask on said first and second element formation regions; a step of etching said oxidation-resist film by using said third mask; a step of forming a fourth mask on said first element formation region and on said first element isolation region by not removing said third mask; a step of forming a second P-type ion implantation layer on said second element isolation region by using said second mask and said fourth mask; a step of removing said third mask and said fourth mask; a step of performing heat treatment to said substrate thereby to form P wells by converting said first P-type ion implantation layers thereto, to form N-type channel stopper by converting said first N-type ion implantation layers thereto, to form a P-type channel stopper by converting said second P-type ion implantation layer thereto and to form a field insulator film in said first and second element isolation regions by using said oxidation-resist film; a step of forming a fifth mask on said P wells; a step of forming a second N-type ion implantation layer in said first element formation region by using said fifth mask; a step of removing said fifth mask; and a step of performing heat treatment to form an N well by said second N-type ion implantation layer.

Claim 13

The manufacturing method of a CMOS integrated circuit as claimed in claim 9, wherein the N-type impurities of said N-type channel stoppers and said N well are phosphorus.

Claim 14

The manufacturing method of a CMOS integrated circuit as claimed in claim 9, wherein the dose of ions used for forming said first N-type ion implantation layers is smaller than the dose of ions used for forming said second ion implantation layer.

Claim 15

The manufacturing method of a CMOS integrated circuit as claimed in claim 9, wherein the dose of ions for forming said first N-type ion-implantation layers is not less than 1×10 12 cm -2 .

Claim 16

A manufacturing method of a CMOS integrated circuit comprising: a step of forming an N + -type buried diffused layer in a region which is to become the element formation region of a P-channel MOS transistor in the upper part on a main surface of a silicon substrate, and forming a P + -type buried implantation layer in a region which is to become the element formation region of an N-channel MOS transistor in the upper part of the main surface of the silicon substrate; a step of forming an N-type silicon epitaxial layer on the main surface of said silicon substrate; a step of forming an SiO 2 film on the surface of said N-type silicon epitaxial layer; a step of forming a first mask on said region which becomes the element formation region of the P-channel MOS transistor and a region which is to become the element isolation region of the P-channel MOS transistor; a step of forming first P-type implantation layers in said region which is to become the element formation region of the N-channel MOS transistor and in a region which is to become the element isolation region of the N-channel MOS transistor, by using said first mask; a step of forming a second mask, by removing said first mask, on said region which is to become the element formation region of the N-channel MOS transistor and on said region which is to become the element isolation region of the N-channel MOS transistor; a step of forming first N-type ion implantation layers in said region which is to become the element formation region of the P-channel MOS transistor and in said region which is to become the element isolation region of the P-channel MOS transistor, by using said second mask; a step of removing said second mask; a step of forming an Si 3 N 4 film all over the top surface; a step of forming a third mask on said region which is to become the element formation region of the N-channel MOS transistor and on said region which is to become the element formation region of the P-channel MOS transistor; a step of etching said Si 3 N 4 film by using said third mask; a step of forming a fourth mask on said region which is to become the element formation region of the P-channel MOS transistor and on said region which is to become the element isolation region of the P-channel MOS transistor, by not removing said third mask; a step of forming a second P-type ion implantation layer on said region which is to become the element isolation region of the N-channel MOS transistor, by using said third mask and said fourth mask; a step of removing said third mask and said fourth mask; a step of performing heat treatment to said silicon substrate thereby to convert said first P-type ion implantation layers to P well, to convert said first N-type ion implantation layers to N-type channel stoppers, to convert said second P-type ion implantation layer to a P-type channel shopper and to form field oxide films in said region which is to become the element isolation region of the N-channel MOS transistor and in said region which is to becomes the element isolation region of the P-channel MOS transistor by suing said Si 3 N 4 film; a step of forming a fifth mask on said P wells; a step of forming a second N-type ion implantation layer on said region which is to become the element formation region of the P-channel MOS transistor, by using said fifth mask; a step of removing said fifth mask; and a step of performing said second N-type ion implantation layer.

Claim 17

A manufacturing method of a CMOS integrated circuit comprising: a step of forming an N + -type buried diffused layer in a region which is to become the element formation region of a P-channel MOS transistor in the upper part on a main surface of a silicon substrate, and forming a P + -type buried implantation layer in a region which is to become the element formation region of an N-channel MOS transistor in the upper part of the main surface of the silicon substrate; a step of forming an N-type silicon epitaxial layer on the main surface of said silicon substrate; a step of forming an SiO 2 film on the surface of said N-type silicon epitaxial layer; a step of forming a first mask on said region which becomes the element formation region of the P-channel MOS transistor and a region which is to become the element isolation region of the P-channel MOS transistor; a step of forming first P-type implantation layers in said region which is to become the element formation region of the N-channel MOS transistor and in a region which is to become the element isolation region of the N-channel MOS transistor, by using said first mask; a step of forming a second mask, by removing said first mask, on said region which is to become the element formation region of the N-channel MOS transistor and on said region which is to become the element isolation region of the N-channel MOS transistor; a step of forming first N-type ion implantation layers in said region which is to become the element formation region of the P-channel MOS transistor and in said region which is to become the element isolation region of the P-channel MOS transistor, by using said second mask; a step of removing said second mask; a step of forming an Si 3 N 4 film all over the top surface; a step of forming a third mask on said region which is to become the element formation region of the N-channel MOS transistor and on said region which is to become the element formation region of the P-channel MOS transistor; a step of etching said Si 3 N 4 film by using said third mask; a step of forming a fourth mask on said region which is to become the element formation region of the P-channel MOS transistor and on said region which is to become the element isolation region of the P-channel MOS transistor, by not removing said third mask; a step of forming a second P-type ion implantation layer on said region which is to become the element isolation region of the N-channel MOS transistor, by using said third mask and said fourth mask; a step of removing said third mask and said fourth mask; a step of performing heat treatment to said silicon substrate thereby to convert said first P-type ion implantation layers to P well, to convert said first N-type ion implantation layers to N-type channel stoppers, to convert said second P-type ion implantation layer to a P-type channel shopper and to form field oxide films in said region which is to become the element isolation region of the N-channel MOS transistor and in said region which is to becomes the element isolation region of the P-channel MOS transistor by suing said Si 3 N 4 film; a step of forming a fifth mask on said P wells; a step of forming a second N-type ion implantation layer on said region which is to become the element formation region of the P-channel MOS transistor, by using said fifth mask; a step of removing said fifth mask; and a step of performing said second N-type ion implantation layer.

Claim 18

The manufacturing method of a CMOS integrated circuit as claimed in claim 13, wherein the N-type impurity of said N-type channel stoppers and said N well is phosphorus.

Claim 19

The manufacturing method of a CMOS integrated circuit as claimed in claim 13, wherein the dose of ions used for forming said first N-type ion implantation layers is smaller than the dose of ions used for forming said second N-type ion implantation layer.

Claim 20

The manufacturing method of a CMOS integrated circuit as claimed in claim 13, wherein the dose of ions used for said first N-type ion implantation layer is not less than 1×10 12 cm 2 .