Method and apparatus for operating a cache memory in a multi-processor

Claim 3

The method of claim 1 wherein said updating comprises replacing a block of data in each said cache memory with said identical block of data from a common memory.

Claim 4

The method of claim 2 wherein said replacing is accomplished by a least recently used (LRU) method.

Claim 5

In a parallel processing computer of the type having a plurality of cache memories, each cache memory associated with one of such processing units, and a common memory associated with said plurality of processing units wherein when a cache memory is tested for referenced data required by an associated processing unit it is updated with a new block of data from said common memory upon determining that said referenced data is not in said cache memory, a method of updating said cache memories comprising the steps of: testing a cache memory for the presence of data to be used in an associated processing unit; in the absence of such data in said cache memory, requesting such data from common memory; and in response to such request, updating each of said cache memories with an identical block of data obtained from said common memory.

Claim 6

In a parallel processing computer of the type having a plurality of cache memories, each cache memory associated with one of such processing units, and a common memory associated with said plurality of processing units wherein when a cache memory is tested for referenced data required by an associated processing unit it is updated with a new block of data from said common memory upon determining that said referenced data is not in said cache memory, a method of updating said cache memories comprising the steps of: testing a cache memory for the presence of data to be used in an associated processing unit; in the absence of such data in said cache memory, requesting such data from common memory; and in response to such request, updating each of said cache memories with an identical block of data obtained from said common memory.

Claim 7

The computer of claim 4 wherein said updating step comprises reading data instructions.

Claim 8

The computer of claim 4 wherein said updating step comprises simultaneously reading said new block of data into each of said cache memories.

Claim 9

A computer comprising: an array of processors operating in parallel with each other; a common memory operatively associated with said array of processors; an array of cache memories, each cache memory operatively associated with one processor within said array of processors, said cache memory providing a miss signal upon the occurrence of miss, means responsive to said miss signal from one cache memory for updating each said cache memory with an identical block of data from said common memory by causing said block of data from common memory to be written to each said cache memory.

Claim 10

A computer comprising: an array of processors operating in parallel with each other; a common memory operatively associated with said array of processors; an array of cache memories, each cache memory operatively associated with one processor within said array of processors, said cache memory providing a miss signal upon the occurrence of miss, means responsive to said miss signal from one cache memory for updating each said cache memory with an identical block of data from said common memory by causing said block of data from common memory to be written to each said cache memory.

Claim 11

The computer of claim 7 wherein said data is instructions.

Claim 12

The computer of claim 7 wherein said means for updating each said cache memory comprises a shared data bus.

Claim 15

The method of claim 10 further comprising the step of selectively updating each cache memory to which said identical block of data is supplied depending on address information associated with said block of data.

Claim 16

In a parallel processing computer of the type having a plurality of processing units operating in parallel, a plurality of cache memories, each cache memory associated with one of such processing units, and a common memory associated with said plurality of processing units wherein when a cache memory is tested for data required by an associated processing unit it is updated with a new block of data from said common memory upon determining that said data is not in said cache memory, a method of updating said cache memories comprising the steps of: testing a cache memory for the presence of data to be used in an associated processing unit; in the absence of such data in said cache memory, requesting such data from common memory; and in response to such request, supplying to each cache memory an identical block of data obtained from said common memory, said block of data providing the data that was absent from the cache memory that was tested.

Claim 17

In a parallel processing computer of the type having a plurality of processing units operating in parallel, a plurality of cache memories, each cache memory associated with one of such processing units, and a common memory associated with said plurality of processing units wherein when a cache memory is tested for data required by an associated processing unit it is updated with a new block of data from said common memory upon determining that said data is not in said cache memory, a method of updating said cache memories comprising the steps of: testing a cache memory for the presence of data to be used in an associated processing unit; in the absence of such data in said cache memory, requesting such data from common memory; and in response to such request, supplying to each cache memory an identical block of data obtained from said common memory, said block of data providing the data that was absent from the cache memory that was tested.

Claim 18

The method of claim 12 further comprising the step of selectively updating each cache memory to which said identical block of data is supplied depending on address information associated with said block of data.

Claim 19

A computer comprising: an array of processors operating in parallel with each other; a common memory operatively associated with said array of processors; an array of cache memories, each cache memory operatively associated with one processor within said array of processors, said cache memory providing a miss signal upon the occurrence of a miss; and means responsive to said miss signal from one cache memory for supplying to each cache memory an identical block of data from said common memory, said block of data providing data absent from the cache memory which provided the miss signal.

Claim 20

A computer comprising: an array of processors operating in parallel with each other; a common memory operatively associated with said array of processors; an array of cache memories, each cache memory operatively associated with one processor within said array of processors, said cache memory providing a miss signal upon the occurrence of a miss; and means responsive to said miss signal from one cache memory for supplying to each cache memory an identical block of data from said common memory, said block of data providing data absent from the cache memory which provided the miss signal.

Claim 21

The apparatus of claim 14 further comprising means associated with each cache memory for selectively updating that cache memory depending on address information associated with said block of data.