US5113440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Universal decoder
Assignee: TV/COM TECHNOLOGIES Inc
•
Filing: 1991-05-15
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Granted: 1992-05-12
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Expires: 2011-05-15
Abstract
Abstract A microprocessor based decoder module for television video signals which have been encoded by suppressing sync pulses and/or inverting picture video. The decoder modules generates sync restoration gates and/or video inversion gates developed from timing signals present in the VBI of the encoded video signal. The VBI timing signals may be either sync pulses which are not suppressed during the VBI, or special timing signals inserted at the video encoder. The microprocessor, in the decoder module, may contain externally selectable program segments where each segment will allow decoding of a different variety of video encoding.
Inventors
- 👤 Ralph P. Harney
- 👤 Michael L. Hightower
- 👤 Anthony J. Wechselberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:44
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/16; H04N7/167; H04N7/171; H04N7/1716; H04N7/1713
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
96 words
A decoder for decoding suppressed sync encoded television video signals in which horizontal sync pulses are suppressed during picture video, said decoder including a microprocessor programmed to determine horizontal sync timing from timing signals in the vertical blanking interval (VBI), means for providing the timing signals in the VBI to the microprocessor, a sync restoration circuit connected to said microprocessor, said microprocessor being further programmed to provide a horizontal sync gate signal, based on the timing signals in the VBI, to said sync restoration circuit whereby said sync restoration circuit restores the suppressed horizontal sync pulses.
Claim 2
Dependent Claim
96 words
A decoder for decoding suppressed sync encoded television video signals in which horizontal sync pulses are suppressed during picture video, said decoder including a microprocessor programmed to determine horizontal sync timing from timing signals in the vertical blanking interval (VBI), means for providing the timing signals in the VBI to the microprocessor, a sync restoration circuit connected to said microprocessor, said microprocessor being further programmed to provide a horizontal sync gate signal, based on the timing signals in the VBI, to said sync restoration circuit whereby said sync restoration circuit restores the suppressed horizontal sync pulses.
Claim 3
Dependent Claim
25 words
The decoder of claim 1 further characterized in that the timing signals in the VBI are unsuppressed horizontal and vertical sync pulses in the VBI.
Claim 4
Dependent Claim
45 words
The decoder of claim 2 further characterized in that said microprocessor is programmed to initiate its timing reconstruction cycle at the beginning of vertical sync timing and to begin the horizontal sync gate signal after the last unsuppressed horizontal sync timing signal in the VBI.
Claim 5
Dependent Claim
32 words
The decoder of claim 3 further characterized in that said microprocessor is programmed to provide a horizontal sync gate signal for each suppressed horizontal sync pulse during a period of picture video.
Claim 6
Dependent Claim
45 words
The decoder of claim 1 further characterized in that horizontal sync pulse may be suppressed during the picture video by a) shifting the level of the horizontal sync pulses of a baseband video signal, or b) attenuating the horizontal sync pulses of a video signal.
Claim 7
Dependent Claim
41 words
The decoder of claim 1 further characterized in that the video encoding includes periodic inversion of video signal polarity, said microprocessor being programmed to detect a video inversion flag and to provide a video inversion gate output as a result thereof.
Claim 8
Dependent Claim
37 words
The decoder of claim 1 further characterized in that the VBI including horizontal and vertical sync pulses in the VBI are suppressed and the timing signals in the VBI are inserted in the VBI during signal encoding.
Claim 9
Dependent Claim
30 words
The decoder of claim 7 further characterized in that said microprocessor is programmed, upon detection of the VBI timing signals, to increase the amplitude of the VBI including sync pulses.
Claim 10
Dependent Claim
44 words
The decoder of claim 8 further characterized in that said microprocessor is programmed to utilize the increased amplitude horizontal sync pulses during each VBI to generate timing for a horizontal sync gate signal to increase the amplitude of horizontal sync pulses during picture video.
Claim 11
Dependent Claim
43 words
The decoder of claim 7 further characterized in that the VBI timing signal consists, in successive horizontal lines, of a plurality of generally equally spaced pulses in a first line and a complement of said plurality of spaced pulses in the succeeding line.
Claim 12
Dependent Claim
61 words
The decoder of claim 10 further characterized in that said VBI timing signal includes, in a horizontal line preceding the first horizontal line having a plurality of spaced pulses, a horizontal line which has a generally constant IRE level over at least a substantial portion thereof, with the IRE level being equal to that of the pulses in the succeeding line.
Claim 13
Dependent Claim
23 words
The decoder of claim 1 further characterized in that the microprocessor has a clock signal which is asynchronous with the received horizontal sync.
Claim 14
Dependent Claim
54 words
The decoder of claim 1 further characterized in that the microprocessor program has multiple segments, each program segment having the capability of recognizing a particular timing signal and providing a horizontal sync restoration gate responsive to a particular version of horizontal sync suppression, said program segments being selectable by means external to the microprocessor.
Claim 15
Independent Claim
90 words
A method of decoding suppressed sync encoded video signals in which horizontal sync is suppressed during picture video, said method including the steps of: obtaining timing signals from the video vertical blanking interval (VBI), providing the timing signals to a microprocessor programmed to determine horizontal sync pulse timing and to provide a horizontal sync gate signal from the timing signals in the VBI, using the microprocessor to provide a horizontal sync gate signal from said timing signals, and using the horizontal sync gate signals to restore suppressed horizontal sync pulses.
Claim 16
Independent Claim
90 words
A method of decoding suppressed sync encoded video signals in which horizontal sync is suppressed during picture video, said method including the steps of: obtaining timing signals from the video vertical blanking interval (VBI), providing the timing signals to a microprocessor programmed to determine horizontal sync pulse timing and to provide a horizontal sync gate signal from the timing signals in the VBI, using the microprocessor to provide a horizontal sync gate signal from said timing signals, and using the horizontal sync gate signals to restore suppressed horizontal sync pulses.
Claim 17
Dependent Claim
34 words
The method of claim 14 further characterized in that the suppressed sync encoded video signals are encoded by either a) shifting the level of horizontal sync pulses or b) attenuating the horizontal sync pulses.
Claim 18
Dependent Claim
25 words
The method of claim 14 further characterized in that the timing signals in the VBI are unsuppressed horizontal and vertical sync pulses in the VBI.
Claim 19
Dependent Claim
23 words
The method of claim 14 further characterized in that the timing signals in the VBI are inserted in the VBI during signal encoding.
References Cited (Backward Citations)
US4019201A
Cited
US4024576A
Cited
US4045814A
Cited
US3919462A
Cited
US4091417A
Cited
US4527195A
Cited
US4322745A
Cited
US4319273A
Cited
JPS57164682A
Cited
US4460922A
Cited
US4484027A
Cited
US4494142A
Cited
US4466017A
Cited
US4494143A
Cited
US4802214A
Cited
US4514761A
Cited
US4575755A
Cited
US4523228A
Cited
US4635112A
Cited
US4628359A
Cited
US4590519A
Cited
US4613901A
Cited
US4563702A
Cited
US4542407A
Cited
US4599647A
Cited
US4554579A
Cited
US4833710A
Cited
US4611242A
Cited
US4703354A
Cited
US4908834A
Cited
US4696034A
Cited
US4712237A
Cited
US4736421A
Cited
US4815129A
Cited
US4739510A
Cited
US4716588A
Cited
US4718086A
Cited
US4712239A
Cited
US4790010A
Cited
US4807286A
Cited
US4839569A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |