Video encoder/decoder system

Claim 2

A video encoder system for processing a video signal on an input terminal having alternate video portions and vertical interval portions, each video portion including video data and horizontal sync pulses, to provide a scrambled video signal on an output terminal, comprising: first encoder means for inverting a plurality of the horizontal sync pulses in a first section of said video signal, said first section including at least part of the video portion and excluding at least part of the vertical interval portion; second encoder means for reducing the amplitude of each said inverted horizontal sync pulses in said first section; and scrambling means for generating a scrambled video signal having said first section of said video signal which has been processed by said first and second encoder means and a second section of said video signal, being that portion of the video signal which has not been processed by said first and second encoder means.

Claim 3

The system of claim 1 wherein said first encoder means includes inverter means for inverting the video portions of the video signal, excluding the vertical interval portions of the video signal.

Claim 4

The system of claim 1 wherein said second encoder means includes amplifying means for reducing the amplitude of the first section of the video signal, including the video and vertical interval portions thereof.

Claim 5

The system of claim 1 wherein said scrambling means comprises switching means in communication with said first and second encoder means and with said input terminal for alternately passing to said output terminal said first section of said video signal which has been processed by said first and second encoder means and said second section of said video signal from said input terminal.

Claim 6

The system of claim 1 and further comprising adjusting means in communication with said first and second encoder means for moving the DC level of said first section of the video signal relative to the DC level of the second section of the video signal to further scramble the video signal and to minimize the power output requirements of the video encoder system.

Claim 7

The system of claim 1 wherein the second section of the video signal not processed by said first and second encoder means comprises at least a part of the vertical sync pulse and a plurality of horizontal sync pulses.

Claim 8

A video encoder system for processing an initial video signal having alternate video portions and vertical interval portions, each video portion including video data and horizontal sync pulses, and each vertical interval portion including a vertical sync pulse, vertical interval dalta, and horizontal sync pulses to provide a scrambled video signal comprising: first encoder means for inverting each at least a part of said video portion; second encoder means for modifying the amplitude of each said video portion including the video data and the horizontal sync pulses; scrambling means for alternately outputting video portions of a modified video signal which have been processed by said first and second encoder means and vertical interval portions of said initial video signal to provide said scrambled video signal; and timing means for detecting the horizontal and vertical sync pulses of said initial video signal and for controlling said scrambling means to provide said scrambled video signal.

Claim 9

A video encoder system for processing an initial video signal having alternate video portions and vertical interval portions, each video portion including video data and horizontal sync pulses, and each vertical interval portion including a vertical sync pulse, vertical interval dalta, and horizontal sync pulses to provide a scrambled video signal comprising: first encoder means for inverting each at least a part of said video portion; second encoder means for modifying the amplitude of each said video portion including the video data and the horizontal sync pulses; scrambling means for alternately outputting video portions of a modified video signal which have been processed by said first and second encoder means and vertical interval portions of said initial video signal to provide said scrambled video signal; and timing means for detecting the horizontal and vertical sync pulses of said initial video signal and for controlling said scrambling means to provide said scrambled video signal.

Claim 10

The encoder system of claim 7 wherein said first encoder means comprises video inverter means for inverting the entire video portion including the video data and the horizontal sync pulses.

Claim 11

The encoder system of claim 7 wherein said second encoder means comprises means for substantially reducing the amplitude of the video portion of the video signal.

Claim 12

The encoder system of claim 7 wherein said scrambling means comprises first input means for receiving a modified video signal which has been processed by said first and second encoder means, second input means for receiving the initial video signal, and switch means for alternately outputting a video portion of the modified video signal and a vertical interval portion of the initial video signal.

Claim 13

The encoder system of claim 10 wherein the timing means comprises a control logic circuit responsive to said vertical and horizontal sync pulses to output a timing pulse to enable the switch means.

Claim 14

A video decoder system for processing a scrambled video signal having an inverted portion including inverted horizontal sync pulses, and a noninverted portion including at least a part of the vertical interval, to provide an unscrambled video signal, the inverted video portion having an amplitude different than the amplitude of the noninverted portion comprising: first decoder means for re-inverting said inverted portion of said scrambled video signal; second decoder means for modifying the amplitude of the reinverted portion of said scrambled video signal to correspond to the amplitude of the noninverted portion; and combining means for generating said unscrambled video signal by alternately outputting the re-inverted portion which has been processed by said first and second decoder means and the noninverted portion of the scrambled video signal.

Claim 15

A video decoder system for processing a scrambled video signal having an inverted portion including inverted horizontal sync pulses, and a noninverted portion including at least a part of the vertical interval, to provide an unscrambled video signal, the inverted video portion having an amplitude different than the amplitude of the noninverted portion comprising: first decoder means for re-inverting said inverted portion of said scrambled video signal; second decoder means for modifying the amplitude of the reinverted portion of said scrambled video signal to correspond to the amplitude of the noninverted portion; and combining means for generating said unscrambled video signal by alternately outputting the re-inverted portion which has been processed by said first and second decoder means and the noninverted portion of the scrambled video signal.

Claim 16

The decoder system of claim 12 wherein said inverted portion includes inverted video data and inverted horizontal sync pulses and wherein the noninverted portion includes the vertical interval of the video signal.

Claim 17

The decoder system of claim 12 wherein said second decoder means comprises means for substantially reducing the reinverted portion of the scrambled video signal.

Claim 18

The decoder system of claim 12 wherein said combining means comprises first input means for receiving the re-inverted portion which has been processed by said first and second decoder means, second input means for receiving the noninverted portion, and switch means for alternately outputting the re-inverted portion and the noninverted portion of the scrambled video signal.

Claim 19

The decoder circuit of claim 15 wherein said timing means comprises control logic means responsive to the vertical and horizontal sync pulses of the unscrambled video signal to generate a timing pulse to enable the switch means.

Claim 20

The decoder circuit of claim 12 wherein the noninverted portion includes a vertical sync pulse and a plurality of horizontal sync pulses, and further comprising timing means for detecting the horizontal and vertical sync pulses of said unscrambled video signal and for controlling the combining means to alternately output said reinverted portions and said noninverted portions.

Claim 21

The decoder circuit of claim 12 wherein the DC level of the inverted portion of the video signal has been offset relative to the noninverted portion, and wherein the DC level of the re-inverted portion is aligned with the DC level of the noninverted portion.

Claim 22

A video encoder system for processing a video signal on an input terminal having alternate video portions and vertical interval portions, each video portion including video data and horizontal sync pulses, and each vertical interval portion including a vertical sync pulse, vertical interval data, and horizontal sync pulses to provide a scrambled video signal on an output terminal, comprising: inverting amplifier means in communication with said input terminal for inverting the video signal and for reducing the amplitude of the input video signal to generate an inverted video signal; switching means in communication with said inverting amplifier means and said input terminal for alternately passing to the output terminal at least a part of the vertical sync pulse and a plurality of the horizontal sync pulses in the vertical interval portion of the input video signal and at least a part of the video portion of the inverted video signal to generate a scrambled video signal; detection means in communication with said input terminal for detecting and transmitting the horizontal and vertical sync pulses of the vertical interval portion; and control means in communication with said detection means and said switching means for generating a control signal for the switching means to generate said scrambled video signal in response to the horizontal and vertical sync pulses transmitted by the detection means to the control means.

Claim 23

A video encoder system for processing a video signal on an input terminal having alternate video portions and vertical interval portions, each video portion including video data and horizontal sync pulses, and each vertical interval portion including a vertical sync pulse, vertical interval data, and horizontal sync pulses to provide a scrambled video signal on an output terminal, comprising: inverting amplifier means in communication with said input terminal for inverting the video signal and for reducing the amplitude of the input video signal to generate an inverted video signal; switching means in communication with said inverting amplifier means and said input terminal for alternately passing to the output terminal at least a part of the vertical sync pulse and a plurality of the horizontal sync pulses in the vertical interval portion of the input video signal and at least a part of the video portion of the inverted video signal to generate a scrambled video signal; detection means in communication with said input terminal for detecting and transmitting the horizontal and vertical sync pulses of the vertical interval portion; and control means in communication with said detection means and said switching means for generating a control signal for the switching means to generate said scrambled video signal in response to the horizontal and vertical sync pulses transmitted by the detection means to the control means.

Claim 24

The video encoder system of claim 19 and further comprising reference detecting means in communication with said inverting amplifier means for detecting a DC reference level of the input video signal and a corresponding DC reference level of the inverted video signal, and adjusting means for shifting the corresponding reference level of the inverted video signal relative to the reference level of the input video signal.

Claim 25

The encoder system of claim 20 wherein said reference detecting means includes first means for detecting the blanking level of the input video signal and second means for detecting the blanking level of the inverted video signal.

Claim 26

The encoder system of claim 21 wherein the adjusting means comprises control means in communication with said second means for generating a control signal to adjust the DC level of the inverted video signal so that the peaks of the horizontal sync pulses of the inverted video signal are substantially at the white reference level of the input video signal.

Claim 27

A video decoder system for processing a scrambled video signal on an input terminal, said scrambled video signal having an encoded section including inverted horizontal sync pulses and inverted video data, and a nonencoded section including at least a part of a vertical interval pulse and a plurality of horizontal sync pulses, to provide an unscrambled video signal on an output terminal, comprising: inverting means in communication with said input terminal for inverting the scrambled video signal to generate an inverted video signal; Amplifier means for increasing the amplitude of the encoded section of the inverted video signal to generate a decoded section of said inverted video section; switching means in communication with the amplifier means and with the input terminal for alternately passing to the output terminal the nonencoded section of the scrambled video signal from the input terminal and the decoded section of the inverted video signal from the inverting means, to generate said unscrambled signal; detection means in communication with said output terminal for detecting and transmitting at least a part of the vertical interval pulse and the plurality of horizontal sync pulses in said nonencoded section; and control means in communication with said detection means and said switching means for generating a control signal for the switching means to provide said unscrambled video signal in response to at least a part of the vertical interval pulse and the plurality of horizontal sync pulses transmitted by said detection means to the control means.

Claim 28

A video decoder system for processing a scrambled video signal on an input terminal, said scrambled video signal having an encoded section including inverted horizontal sync pulses and inverted video data, and a nonencoded section including at least a part of a vertical interval pulse and a plurality of horizontal sync pulses, to provide an unscrambled video signal on an output terminal, comprising: inverting means in communication with said input terminal for inverting the scrambled video signal to generate an inverted video signal; Amplifier means for increasing the amplitude of the encoded section of the inverted video signal to generate a decoded section of said inverted video section; switching means in communication with the amplifier means and with the input terminal for alternately passing to the output terminal the nonencoded section of the scrambled video signal from the input terminal and the decoded section of the inverted video signal from the inverting means, to generate said unscrambled signal; detection means in communication with said output terminal for detecting and transmitting at least a part of the vertical interval pulse and the plurality of horizontal sync pulses in said nonencoded section; and control means in communication with said detection means and said switching means for generating a control signal for the switching means to provide said unscrambled video signal in response to at least a part of the vertical interval pulse and the plurality of horizontal sync pulses transmitted by said detection means to the control means.

Claim 29

The video decoder system of claim 23 and further comprising amplifier means for increasing the amplitude of the encoded section of the inverted video signal to correspond with the amplitude of the nonencoded section of the scrambled video signal.

Claim 30

The video decoder system of claim 24 and further comprising comparator means for detecting a DC reference level of the input scrambled video signal and a corresponding DC reference level of the inverted video signal, and adjusting means for shifting the corresponding DC reference level of the inverted video signal to substantially align it with the DC reference level of the input scrambled video signal.

Claim 33

The method of claim 26 wherein second section of said video signal includes at least part of the vertical sync pulse and a plurality of horizontal sync pulses.

Claim 34

The method of claim 26 wherein the DC level of the first section is shifted relative to the DC level of the second section of the video signal.

Claim 37

The method of claim 29 wherein said noninverted vertical interval portion includes at least a part of a vertical sync pulse and a plurality of horizontal sync pulses, and further comprising the step of detecting the horizontal and vertical sync pulses of said scrambled video signal to determine the timing for generating said unscrambled video signal.

Claim 40

The method of claim 31 wherein each field of the video signal comprises a video information section and a vertical interval section and wherein said inverted portion of the video signal comprises at least part of the video information section and excludes at least part of the vertical interval section.

Claim 41

The method of claim 32 wherein said inverted portion of the video signal comprises all of the video information section and wherein said noninverted portion of the video signal comprises all of the vertical interval section.

Claim 42

The method of claim 31 wherein each field has a second DC voltage reference level and wherein the inverted portion is shifted to lie substantially between the first and second reference levels of the noninverted portion.

Claim 43

The method of claim 31 wherein the inverted second reference level of said inverted portion is substantially aligned with the first reference level of the noninverted portion.

Claim 44

The method of claim 31 wherein each field of the video signal includes a plurality of horizontal sync pulses and wherein the tips of the inverted horizontal sync pulses of the inverted portion are substantially aligned with second reference level of the noninverted portion.

Claim 45

The method of claim 31 wherein the first DC voltage reference level of the video signal is the blanking level.

Claim 46

The method of claim 31 wherein the DC voltage second reference level of the video signal is the white level.

Claim 49

The method of encoding of claim 39 wherein the second predetermined amount of shifting substantially aligns the inverted horizontal sync tip level of the inverted portion with the white level of the noninverted portion.

Claim 50

The method of encoding of claim 39 wherein the second predetermined amount of shifting substantially aligns the inverted white level of the inverted portion with the blanking level of the noninverted portion.

Claim 51

A video encoding system for encoding a normalized video signal having periodic video fields, each field having a first DC voltage reference level, comprising: first encoding means for inverting aportion of each field of the video signal to provide an inverted portion and a noninverted portion of the video signal, second encoding means for reducing the amplitude of said inverted portion of the video signal by a first predetermined amount; means for determining the first DC voltage reference levels of said inverted portion and said noninverted portion; and control means for shifting the inverted portion relative to the noninverted portion so that the first DC reference level of the inverted portion is offset by a second predetermined amount from the first DC reference level of the noninverted portion of the video signal.

Claim 52

A video encoding system for encoding a normalized video signal having periodic video fields, each field having a first DC voltage reference level, comprising: first encoding means for inverting aportion of each field of the video signal to provide an inverted portion and a noninverted portion of the video signal, second encoding means for reducing the amplitude of said inverted portion of the video signal by a first predetermined amount; means for determining the first DC voltage reference levels of said inverted portion and said noninverted portion; and control means for shifting the inverted portion relative to the noninverted portion so that the first DC reference level of the inverted portion is offset by a second predetermined amount from the first DC reference level of the noninverted portion of the video signal.

Claim 53

The encoding system of claim 42 wherein each field of the video signal comprises a video information section and a vertical interval section and wherein said inverted portion of the video signal comprises at least part of the video information section and excludes at least part of the vertical interval section.

Claim 54

The system of claim 43 wherein said inverted portion of the video signal comprises all of the video information section and wherein said noninverted portion of the video signal comprises all of the vertical interval section.

Claim 55

The system of claim 42 and further comprising second determining means for determining a second DC voltage reference of said inverted portion and said noninverted portion, and wherein said control means shifts the inverted portion to lie substantially between the first and second reference levels of the noninverted portion.

Claim 56

The system of claim 42 wherein the inverted second reference level of said inverted portion is substantially aligned with the first reference level of the noninverted portion.

Claim 57

The system of claim 42 wherein each field of the video signal includes a plurality of horizontal sync pulses and further comprising third determining means for determining the tips of the inverted horizontal sync pulses and wherein said control means shifts the inverted portion so that the tips of the inverted horizontal sync pulses of the inverted portion are substantially aligned with second reference level of the noninverted portion.

Claim 58

The system of claim 42 wherein the first DC voltage reference level of the video signal is the blanking level.

Claim 59

The system of claim 42 wherein the second DC voltage reference level of the video signal is the white level.

Claim 62

The decoding method of claim 50 wherein said first DC voltage reference level is the blanking level.

Claim 63

A video decoding system for decoding a normalized scrambled video signal having periodic video fields, each field having an inverted portion and a noninverted portion with an amplitude greater than the inverted portion and a first DC voltage reference level relative to each of the inverted and noninverted portions, comprising first decoding means for inverting said inverted portion of the scrambled video signal to generate a re-inverted portion; second decoding means for increasing the amplitude of the reinverted portion to correspond to the amplitude of the noninverted portion of the scrambled video signal; means for determining the first DC voltage reference levels of the re-inverted portion and the noninverted portion; and control means for shifting the re-inverted portion relative to the noninverted portion by a predetermined amount so that the DC reference levels of the re-inverted portion and noninverter portion are substantially aligned.

Claim 64

A video decoding system for decoding a normalized scrambled video signal having periodic video fields, each field having an inverted portion and a noninverted portion with an amplitude greater than the inverted portion and a first DC voltage reference level relative to each of the inverted and noninverted portions, comprising first decoding means for inverting said inverted portion of the scrambled video signal to generate a re-inverted portion; second decoding means for increasing the amplitude of the reinverted portion to correspond to the amplitude of the noninverted portion of the scrambled video signal; means for determining the first DC voltage reference levels of the re-inverted portion and the noninverted portion; and control means for shifting the re-inverted portion relative to the noninverted portion by a predetermined amount so that the DC reference levels of the re-inverted portion and noninverter portion are substantially aligned.

Claim 65

The video decoding system of claim 52 wherein said first DC voltage reference level is the blanking level.