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US5113371A
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Semiconductor memory apparatus with a spare memory cell array
Assignee: NEC Corp
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Filing: 1990-07-26
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Granted: 1992-05-12
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Expires: 2010-07-26
Abstract
Abstract In a test of a fabricated semiconductor memory chip, a test control signal is supplied to a test control circuit, so that a spare memory cell array is tested whether spare memory cells are functionable for writing and reading of data. The test control signal is applied to terminals which are used for the supplying of an address signal, etc. For this purpose, the test control signal has a level different from that of the address signal. Therefore, the spare memory cell array can be tested simultaneously with a test of normal memory cell array.
Inventors
- 👤 Mitsuhiro Hamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:37
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
201 words
A semiconductor memory apparatus with a spare memory cell array, comprising: a normal memory cell array including normal memory cells arranged in a predetermined pattern, data being written into said normal memory cells and read therefrom; a spare memory cell array including spare memory cells arranged in a predetermined pattern, data being written into at least one of said spare memory cells and read therefrom, when at least one of said normal memory cells is faulty; terminals for supplying an address signal to an address signal decoder for said normal memory cell array; an address buffer for holding said address signal to be supplied to said decoder; a faulty address detecting circuit for generating a selecting signal to select said at least one of said spare memory cells, when said address signal held by said address buffer is an address of a faulty normal memory cell; and a test control circuit for selecting said spare memory cells to be enabled for writing and reading of data, and inhibiting said normal memory cells to be enabled by receiving a test control signal supplied from said terminals, said test control signal being of a logic level different from that of said address signal.
Claim 2
Dependent Claim
201 words
A semiconductor memory apparatus with a spare memory cell array, comprising: a normal memory cell array including normal memory cells arranged in a predetermined pattern, data being written into said normal memory cells and read therefrom; a spare memory cell array including spare memory cells arranged in a predetermined pattern, data being written into at least one of said spare memory cells and read therefrom, when at least one of said normal memory cells is faulty; terminals for supplying an address signal to an address signal decoder for said normal memory cell array; an address buffer for holding said address signal to be supplied to said decoder; a faulty address detecting circuit for generating a selecting signal to select said at least one of said spare memory cells, when said address signal held by said address buffer is an address of a faulty normal memory cell; and a test control circuit for selecting said spare memory cells to be enabled for writing and reading of data, and inhibiting said normal memory cells to be enabled by receiving a test control signal supplied from said terminals, said test control signal being of a logic level different from that of said address signal.
Claim 3
Dependent Claim
66 words
A semiconductor memory apparatus with a spare memory cell array, according to claim 1, wherein: said address buffer is of an ECL circuit; said address signal is of an ECL level; and said test control signal has a high level which is higher than a high level of said ECL level and a low level which is lower than a low level of said ECL level.
Claim 4
Dependent Claim
80 words
A semiconductor memory apparatus with a spare memory cell array, according to claim 1, wherein: said faulty address detecting circuit, comprises: means for storing an address of a faulty memory cell in said normal memory cell array; means for comparing said address signal held by said address buffer with said address of said faulty memory cell; and means for generating said selecting signal, when said address signal held by said address buffer is said address of said faulty memory cell.
References Cited (Backward Citations)
US4567580A
Cited
US4860260A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |