Dynamic random access memory

Claim 1

A dynamic random access memory cell, comprising: a semiconductor substrate of a first conduction type; a transfer transistor formed on said semiconductor substrate, said transfer transistor comprising first and second impurity diffusion layers of a second conduction type separately formed on a surface of said semiconductor substrate with a predetermined distance therebetween, a gate insulation layer covering an area between said first and second impurity diffusion layers, a gate electrode formed on said gate insulation layer; a trench structure provided into said semiconductor substrate in which a capacitor insulation layer is formed along a wall of said trench structure; a buried impurity diffusion layer of a second conduction type formed below a bottom of said trench structure to touch said capacitor insulation layer and to have a predetermined vertical distance from said second impurity diffusion layer, a potential level of said buried impurity diffusion layer being fixed at a high level; an accumulation node layer formed on said trench structure to cover said capacitor insulation layer, said accumulation node layer being connected ohmically with said second impurity diffusion layer; wherein said second impurity diffusion layer, said buried impurity diffusion layer, said capacitor insulation layer and said accumulation node layer comprise a vertical transistor; said accumulation node layer accumulates charges transferred from said first impurity diffusion layer through said transfer transistor which has been excited to an ON state; and said vertical transistor is excited to an ON state when a potential level of said accumulating node layer is high, and an OFF state of said vertical transistor occurs when a potential level of said accumulation node layer is low.