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US5113093A
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Semiconductor integrated circuit with multiple operation
Assignee: Mitsubishi Electric Corp
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Filing: 1990-07-10
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Granted: 1992-05-12
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Expires: 2010-07-10
Abstract
Abstract When the reset input changes 0 V to Vcc, predetermined operational mode control information is set in an operational mode register (11) to establish a user operational mode. When the reset input changes from 0 V to 2 Vcc, the operational mode control information inputted to a predetermined terminal of the input/output port (25, 58) is set in the operational mode control unit (10a, 10b) to establish a test or other mode.
Inventors
- 👤 Tetsu Tashiro
- 👤 Minoru Takeuchi
- 👤 Yoshiyuki Ishimaru
- 👤 Shinichi Hirose
- 👤 Kazuo Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
96 words
A semiconductor integrated circuit responsive to operational mode control information set in an operational mode setting unit to set a plurality of operational modes such as user and test modes, characterized by operational mode control means for setting a predetermined operational mode control information in said operational mode setting unit at a transitional edge of a reset input when said reset input takes a first level change and operational mode control information inputted at a predetermined terminal of an input/output terminal in said operation mode setting unit when said reset input takes a second level change.
Claim 2
Dependent Claim
96 words
A semiconductor integrated circuit responsive to operational mode control information set in an operational mode setting unit to set a plurality of operational modes such as user and test modes, characterized by operational mode control means for setting a predetermined operational mode control information in said operational mode setting unit at a transitional edge of a reset input when said reset input takes a first level change and operational mode control information inputted at a predetermined terminal of an input/output terminal in said operation mode setting unit when said reset input takes a second level change.
Claim 3
Dependent Claim
96 words
The semiconductor integrated circuit of claim 1, wherein said operational mode setting unit consists of a register and said operational mode control means comprises: a level decision circuit for deciding reset signals from reset input terminal to set a predetermined operational mode control information in said operational mode register for said first level change; and a mode setting control circuit for setting operational mode control information inputted at a predetermined terminal of said input/output port in said operation mode register when said level decision circuit recognized that said reset input is in said second level change.
Claim 4
Dependent Claim
102 words
A semiconductor integrated circuit responsive to operation mode control information set in an operation mode setting unit to set a plurality of operation modes such as user and test modes, characterized by: operational mode control means for setting a predetermined operational mode control information in said operation mode setting unit at a transitional edge of a reset input when said reset input is in a first level change and operational mode control information inputted from a predetermined terminal of an input/output port via an internal data bus in said operational mode setting unit when said reset input is a second level change.
Claim 5
Dependent Claim
102 words
A semiconductor integrated circuit responsive to operation mode control information set in an operation mode setting unit to set a plurality of operation modes such as user and test modes, characterized by: operational mode control means for setting a predetermined operational mode control information in said operation mode setting unit at a transitional edge of a reset input when said reset input is in a first level change and operational mode control information inputted from a predetermined terminal of an input/output port via an internal data bus in said operational mode setting unit when said reset input is a second level change.
Claim 6
Dependent Claim
103 words
The semiconductor integrated circuit of claim 3, wherein said operational mode setting unit consists of a register and said operational mode control means comprises: a level decision circuit for deciding levels of reset signals from reset input terminal and sets a predetermined operational mode control information in said operational mode register for said first level change; and a mode setting control circuit for setting operational mode control information inputted from a predetermined terminal of said input/output port via an internal data bus in said operation mode register when said level decision circuit recognizes that said reset input is in said second level change.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-12 | 1995-11-11 | 1996-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-12 | 1999-11-11 | 2000-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-12 | 2003-11-11 | 2004-05-12 | $7700.00 | Window Closed / Lapsed |