Patent US5111429A successfully refreshed from Google Patents.
US5111429A
Expired / Lapsed
US
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Single event upset hardening CMOS memory circuit
Assignee: Idaho Research Foundation Inc
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Filing: 1990-11-06
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Granted: 1992-05-05
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Expires: 2010-11-06
Abstract
Abstract A CMOS storage cell includes an n-channel storage circuit which has cross coupled n-channel storage transistors and a p-channel storage circuit including cross coupled p-channel storage transistors. Each of the n-channel storage transistors has an n-channel load transistor and each of the p-channel storage transistors has a p-channel load transistor. The n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit. The n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors. The storage cell can be used for a Static RAM or for a flip flop.
Inventors
- 👤 Sterling R. Whitaker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:14
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; H03K3/356104; H03K3/356113; H03K3/356147; H03K3/356156
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
48 words
A cross coupled storage cell for a single binary bit of information comprising: a) first cross coupled means for storing the bit; b) second cross coupled means for storing the bit; and c) means for cross coupling the first cross coupled means to the second cross coupled means.
Claim 2
Dependent Claim
48 words
A cross coupled storage cell for a single binary bit of information comprising: a) first cross coupled means for storing the bit; b) second cross coupled means for storing the bit; and c) means for cross coupling the first cross coupled means to the second cross coupled means.
Claim 3
Dependent Claim
24 words
The apparatus according to claim 1 wherein the first cross coupled means comprises all n-channel transistors and the second means comprises all p-channel transistors.
Claim 4
Dependent Claim
414 words
The apparatus according to claim 2 wherein each of the transistors has a source, a drain and a gate a) wherein the first cross coupled means comprises: 1) a first n-channel storage node and a second n-channel storage node; 2) a first n-channel storage transistor having its drain coupled to the first n-channel storage node and its source couple to a ground potential; 3) a second n-channel storage transistor having its drain coupled to the first n-channel storage node and its source coupled to the ground potential; 4) a first n-channel load transistor having its drain coupled to a power supply potential and its source coupled to the first n-channel storage node; and 5) a second n-channel load transistor having its drain coupled to the power supply potential and its source coupled to the second n-channel storage node; 6) the gate of the first n-channel storage transistor is coupled to the second n-channel storage node; and 7) the gate of the second n-channel transistor is coupled to the first n-channel storage node; b) wherein the second cross coupled means comprises: 1) a first p-channel storage node and a second p-channel storage node; 2) a first p-channel storage transistor having its source coupled to the first storage node and its drain coupled to the power supply potential; 3) a second p-channel storage transistor having its source coupled to the first storage node and its drain coupled to the power supply potential; 4) a first p-channel load transistor having its source coupled to the ground supply potential and its drain coupled to the first p-channel storage node; and 5) a second p-channel load transistor having its source coupled to the ground potential and its drain source coupled to the second p-channel storage node; 6) the gate of the first n-channel storage transistor is coupled to the second n-channel storage node; and 7) the gate of the second n-channel transistor is coupled to the first n-channel storage node; and c) wherein the means for cross coupling the first cross coupled means to the second cross coupled means comprises: 1) the gate of the first n-channel load transistor is coupled to the first p-channel storage node; 2) the gate of the second n-channel load transistor is coupled to the second p-channel storage node; 3) the gate of the first p-channel load transistor is coupled to the first n-channel storage node; and 4) the gate of the second p-channel load transistor is coupled to the second n-channel storage node.
Claim 5
Dependent Claim
38 words
The apparatus according to claim 3 wherein the p-channel load transistors are designed to carry less current than the n-channel storage transistors and the n-channel load transistors are designed to carry less current than the p-channel storage transistors.
Claim 6
Dependent Claim
15 words
The apparatus according to claim 4 wherein the storage cell is for a Static RAM.
Claim 7
Dependent Claim
15 words
The apparatus according to claim 4 wherein the storage cell is for a flip flop.
Claim 8
Dependent Claim
70 words
A CMOS storage cell comprising: a) an n-channel storage circuit including cross coupled n-channel storage transistors each having an n-channel load transistor; and b) a p-channel storage circuit including cross coupled p-channel storage transistors each having an n-channel load transistor, wherein the n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit.
Claim 9
Dependent Claim
70 words
A CMOS storage cell comprising: a) an n-channel storage circuit including cross coupled n-channel storage transistors each having an n-channel load transistor; and b) a p-channel storage circuit including cross coupled p-channel storage transistors each having an n-channel load transistor, wherein the n-channel load transistors are coupled to be controlled by the p-channel storage circuit and the p-channel load transistors are coupled to be controlled by the n-channel storage circuit.
Claim 10
Dependent Claim
38 words
The apparatus according to claim 7 wherein the n-channel load transistors are designed to carry less current than the p-channel storage transistors and the p-channel load transistors are designed to carry less current than the n-channel storage transistors.
Claim 11
Dependent Claim
15 words
The apparatus according to claim 8 wherein the storage cell is for a Static RAM.
Claim 12
Dependent Claim
15 words
The apparatus according to claim 8 wherein the storage cell is for a flip flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-05 | 1995-11-04 | 1996-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-05 | 1999-11-04 | 2000-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-05 | 2003-11-04 | 2004-05-05 | $7700.00 | Window Closed / Lapsed |