Fabrication of personalizable integrated circuits

Claim 2

A gate array device comprising: a collection of semiconductor elements; fusible links interconnecting the collection of semiconductor elements into an inoperably connected gate array device; and an insulation layer disposed over said collection of semiconductor elements and having discrete apertures overlying said fusible links, said collection of semiconductor elements being interconnected for converting the inoperable gate array device into a selected operable electronic function upon the fusing of predetermined ones of the fusible links.

Claim 3

A gate array device according to claim 1 and wherein said semiconductor elements comprise transistors formed on a silicon substrate.

Claim 4

A gate array device according to claim 1 and wherein said fusible links comprise a first plurality of connection links operative to provide a plurality of connections between individual semiconductor elements to define functional groupings thereof and a second plurality of connection links operative to provide a plurality of connections between functional groupings.

Claim 5

A gate array device according to claim 2 and wherein said gate array device includes a least two metal layers and fusible links formed on each of said at least two metal layers.

Claim 6

A gate array device according to claim 3 and wherein said gate array device includes at least two metal layers and said fusible links including fusible links formed on each of said at least two metal layers.

Claim 7

An integrated circuit device comprising: a substrate; a collection of cells mounted on the substrate having input/output pins for operating the integrated circuit device; a plurality of fusible links connecting the cells into an inoperable circuit device; and an insulation layer disposed over said collection of cells and having discrete apertures overlying said fusible links, said plurality of fusible links being without electrical fusing connections capable of fusing by electrical current supplied through the input/output pins of the integrated circuit, said collection of cells being interconnected for converting the inoperable circuit device into an operable circuit device upon fusing of predetermined ones of said plurality of links.

Claim 8

An integrated circuit device comprising: a substrate; a collection of cells mounted on the substrate having input/output pins for operating the integrated circuit device; a plurality of fusible links connecting the cells into an inoperable circuit device; and an insulation layer disposed over said collection of cells and having discrete apertures overlying said fusible links, said plurality of fusible links being without electrical fusing connections capable of fusing by electrical current supplied through the input/output pins of the integrated circuit, said collection of cells being interconnected for converting the inoperable circuit device into an operable circuit device upon fusing of predetermined ones of said plurality of links.

Claim 9

An integrated circuit according to claim 6 and wherein said integrated circuit comprises a gate array.

Claim 10

An integrated circuit device according to claim 5 and wherein said integrated circuit device includes at least two metal layers and said fusible links including fusible links formed on each of said at least two metal layers.

Claim 11

A integrated circuit device according to claim 6 and wherein said gate array device includes at least two metal layers and said fusible links including fusible links formed in each of said at least two metal layers.

Claim 12

A customized gate array device comprising: a collection of semiconductor elements; fusible links interconnecting the collection of semiconductor elements into an inoperably connected gate array device; and an insulation layer disposed over said collection of semiconductor elements and having discrete apertures overlying said fusible links, said collection of semiconductor elements being interconnected and selected ones of said fusible links being fused, thereby converting the inoperable gate array device into a selected operable electronic function.

Claim 13

A customized gate array device comprising: a collection of semiconductor elements; fusible links interconnecting the collection of semiconductor elements into an inoperably connected gate array device; and an insulation layer disposed over said collection of semiconductor elements and having discrete apertures overlying said fusible links, said collection of semiconductor elements being interconnected and selected ones of said fusible links being fused, thereby converting the inoperable gate array device into a selected operable electronic function.

Claim 14

An integrated circuit device according to claim 27 and wherein said gate array device includes at least two metal layers and said fusible links including fusible links formed on each of said at least two metal layers.