US5111085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digitally controlled delay circuit
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1987-04-29
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Granted: 1992-05-05
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Expires: 2007-04-29
Abstract
Abstract A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.
Inventors
- 👤 John W. Stewart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:55
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/133; H03K2005/00013; H03K2005/00019; H03K2005/00058; H03K2005/00065; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
153 words
A delay circuit comprising: a first resistance; an inverter circuit coupled between a first voltage source and a reference potential by said first resistance for receiving a signal to be delayed; a plurality of different size resistances connectable in parallel to said first resistance; a distributed capacitance circuit coupled to the output of said inverter circuit so that current flows between said inverter circuit and said distributed capacitance circuit and charges the capacitance of said distributed capacitance circuit, said distributed capacitance circuit inverting the signal on the output of said inverter circuit and providing a signal delay as a function of the charging of the capacitance of said distributed capacitance circuit; and means for selecting one of said plurality of different size resistances to be actively connected in parallel with said first resistance, so that the amount of the current available to charge the capacitance of said distributed capacitance current may be increased.
Claim 2
Dependent Claim
153 words
A delay circuit comprising: a first resistance; an inverter circuit coupled between a first voltage source and a reference potential by said first resistance for receiving a signal to be delayed; a plurality of different size resistances connectable in parallel to said first resistance; a distributed capacitance circuit coupled to the output of said inverter circuit so that current flows between said inverter circuit and said distributed capacitance circuit and charges the capacitance of said distributed capacitance circuit, said distributed capacitance circuit inverting the signal on the output of said inverter circuit and providing a signal delay as a function of the charging of the capacitance of said distributed capacitance circuit; and means for selecting one of said plurality of different size resistances to be actively connected in parallel with said first resistance, so that the amount of the current available to charge the capacitance of said distributed capacitance current may be increased.
Claim 3
Dependent Claim
36 words
The delay circuit according to claim 1 wherein each of said plurality of different size resistances is a MOS transistor, having a gate electrode for receiving a signal for selecting said transistor into an on state.
Claim 4
Dependent Claim
19 words
The delay circuit according to claim 1 wherein said inverter circuit is comprised of a two transistor CMOS inverter.
Claim 5
Dependent Claim
24 words
The delay circuit according to claim 1 wherein said first resistance is a MOS transistor, having a gate electrode connected to said voltage source.
Claim 6
Dependent Claim
33 words
The delay circuit according to claim 1 wherein said distributed capacitance circuit is comprised of a second inverter circuit and a third inverter circuit having a means for resetting a cascaded delay circuit.
Claim 7
Dependent Claim
109 words
A delay circuit comprising: a first inverter circuit for receiving and inverting a signal to be delayed and providing the inverted signal at its output, said first inverter circuit coupled between a voltage source and a reference potential by a first resistance; a plurality of different size resistances coupled in parallel to said first resistance means for selectively decreasing the value of said first resistance; and a second inverter circuit including distributed capacitance coupled to said first inverter circuit and to said voltage source for inverting and delaying the inverted signal at the output of said first inverter circuit as a function of current flowing through the first resistance.
Claim 8
Dependent Claim
109 words
A delay circuit comprising: a first inverter circuit for receiving and inverting a signal to be delayed and providing the inverted signal at its output, said first inverter circuit coupled between a voltage source and a reference potential by a first resistance; a plurality of different size resistances coupled in parallel to said first resistance means for selectively decreasing the value of said first resistance; and a second inverter circuit including distributed capacitance coupled to said first inverter circuit and to said voltage source for inverting and delaying the inverted signal at the output of said first inverter circuit as a function of current flowing through the first resistance.
Claim 9
Dependent Claim
18 words
The delay circuit according to claim 6 wherein said first inverter circuit is a two transistor CMOS inverter.
Claim 10
Dependent Claim
24 words
The delay circuit according to claim 6 wherein said first resistance is a MOS transistor having a gate electrode connected to said voltage source.
Claim 11
Dependent Claim
20 words
The delay circuit according to claim 1, wherein said distributed capacitance circuit is comprised of a two transistor CMOS inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-05 | 1995-11-04 | 1996-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-05 | 1999-11-04 | 2000-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-05 | 2003-11-04 | 2004-05-05 | $7700.00 | Window Closed / Lapsed |