Patent US5110752A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5110752A Expired / Lapsed US ⏱️ 0.0 years remaining

Roughened polysilicon surface capacitor electrode plate for high denity dram

Assignee: INDUSTRIAL TECHNOLOGYY
•
Filing: 1991-07-10
•
Granted: 1992-05-05
•
Expires: 2011-07-10
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of fabricating a microminaturized capacitor having an electrode that is roughened to increase the effective area per unit area and resulting structure, particularly adapted for use in high density dynamic random access memory devices. The method involves depositing a conductive polycrystalline silicon layer. The depositing a metal such as a refractory metal over the polysilicon layer. The composite layer is heated to form a metal silicide and roughened polycrystalline silicon surface while the grains also grow large. The metal silicide is removed, leaving a roughened surface. The capacitor dielectric layer is deposited upon the roughened surface. The second conductive polycrystalline silicon layer is now formed upon said dielectric layer to complete the capacitor.

Inventors

  • 👤 Chih-Yuan Lu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 11:12
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; Y; Y10; Y10S; Y10S438/00; Y10S438/964

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 164 words
A method to produce a roughened surface capacitor fabricated on a monocrystalline semiconductor substrate comprising: depositing a thin first polycrystalline silicon layer to form a first capacitor plate on a particularly completed DRAM over a base insulating layer and a contact opening exposing said substrate; doping said first polycrystalline silicon layer with an impurity for semiconductors; depositing a thin layer of a metal capable of forming a silicide over the surface of said first layer; heating the resultant composite layer at a temperature to cause silicidation for a time sufficient to preferentially react with grains versus grain boundaries and to grow silicon grain crystals on the surfaces to thereby producing a roughened surface; removing the metal silicide from the resultant roughened composite layer with a suitable etchant; depositing a thin insulating layer to form a capacitor dielectric layer over the surface of the roughened layer; and depositing a second thin polycrystalline silicon layer over said thin insulating layer to form the second capacitor plate.
Claim 2
Independent Claim 164 words
A method to produce a roughened surface capacitor fabricated on a monocrystalline semiconductor substrate comprising: depositing a thin first polycrystalline silicon layer to form a first capacitor plate on a particularly completed DRAM over a base insulating layer and a contact opening exposing said substrate; doping said first polycrystalline silicon layer with an impurity for semiconductors; depositing a thin layer of a metal capable of forming a silicide over the surface of said first layer; heating the resultant composite layer at a temperature to cause silicidation for a time sufficient to preferentially react with grains versus grain boundaries and to grow silicon grain crystals on the surfaces to thereby producing a roughened surface; removing the metal silicide from the resultant roughened composite layer with a suitable etchant; depositing a thin insulating layer to form a capacitor dielectric layer over the surface of the roughened layer; and depositing a second thin polycrystalline silicon layer over said thin insulating layer to form the second capacitor plate.
Claim 3
Dependent Claim 30 words
The method of claim 1 wherein said first polycrystalline silicon layer is doped with an impurity in a concentration of between about 10 18 to 10 21 cm 3 .
Claim 4
Dependent Claim 31 words
The method of claim 1 wherein said impurity is introduced into said first layer by combining it with the reactant for depositing the said first layer as the layer is deposited.
Claim 5
Dependent Claim 17 words
The method of claim 1 wherein said impurity is introduced into said first layer by ion implantation.
Claim 6
Dependent Claim 15 words
The method of claim 1 wherein said metal is a refractory metal and is titanium.
Claim 7
Dependent Claim 20 words
The method of claim 5 wherein the thickness of said layer of titanium is between about 400 to 2000 Angstroms.
Claim 8
Dependent Claim 25 words
The method of claim 5 wherein the composite layer of titanium and polycrystalline silicon is heated to a temperature between about 500° to 1000° C.
Claim 9
Dependent Claim 26 words
The method of claim 7 wherein said composite layer is heated for a time in the range of 10 to 180 minutes in an inert atmosphere.
Claim 10
Dependent Claim 20 words
The method of claim 5 wherein the resultant layer of titanium disilicide is removed by a buffered hydrofluoric acid solution.
Claim 11
Dependent Claim 10 words
The method of claim 1 wherein said metal is cobalt.
Claim 12
Dependent Claim 10 words
The method of claim 1 wherein said metal is tungsten.
Claim 13
Dependent Claim 20 words
The method of claim 1 wherein the thickness of said thin insulating layer is between about 30 to 250 Angstroms.
Claim 14
Dependent Claim 22 words
The method of claim 12 wherein the thin insulating layer is a composite layer of silicon oxide, silicon nitride and silicon oxide.
Claim 15
Dependent Claim 15 words
The method of claim 12 wherein the thin insulating layer at least includes tantalum oxide.
Claim 16
Dependent Claim 21 words
The method of claim 12 wherein the thickness of said second polycrystalline silicon layer is between about 500 to 3000 Angstroms.
Claim 17
Dependent Claim 32 words
The method of claim 1 wherein said roughened surface capacitor is made in combination with a field effect transistor and is adapted for use in a high density dynamic random access memory.
Claim 18
Dependent Claim 28 words
The method of claim 1 wherein following said removal of said metal silicide layer, the said first polycrystalline silicon layer is patterned as an electrode of said capacitor.

References Cited (Backward Citations)

JPH023557A Cited
JPH0265267A Cited
US5043780A Cited
US5049517A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-05-05 1995-11-04 1996-05-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-05-05 1999-11-04 2000-05-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-05-05 2003-11-04 2004-05-05 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag