US5109488A
Expired / Lapsed
US
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Data processing system buffering sequential data for cyclically recurrent delay times, memory address generator for use in such system
Assignee: IPG Electronics 503 Ltd
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Filing: 1989-02-28
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Granted: 1992-04-28
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Expires: 2009-02-28
Abstract
Abstract A data processing system buffers sequential data for the duration of cyclically recurrent delay times. Memory location allocation is performed in such a way, that the memory is used efficiently without data-shifting after a read-out, and that the address generator is fairly simple.
Inventors
- 👤 Hendrik Dijkstra
- 👤 Cornelis M. Huizer
- 👤 Robert J. Sluijter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:28
CPC Classifications
G; G06; G06F; G06F12/00; G06F7/00; G06F7/76; G06F7/78; G06F7/785
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
200 words
A data processing system comprising a) a data input for receiving sequential data units; b) a data output; c) a memory coupled between the data input and the data output and having a plurality of memory locations, for buffering a respective next data unit for the duration of a respective next time delay in a recurrent cycle of time delays; d) a memory address generator coupled to the memory for generating for each respective memory location a respective sequence of time slots, wherein i) each respective time slot starts with an associated write instruction for the respective memory location and terminates with an associated last read instruction for the respective memory location; ii) each respective time slot is representative of the respective time delay; iii) each sequence of time slots is periodic with a period consisting of a first permutation of time slots, the first permutation being indicative of a second permutation of the delay times per cycle; iv) in each first permutation the next time slot is the time slot that has its write instruction executed the earliest with regard to the remaining time slots in the first permutation; and v) the sequences are mutually staggered by one cycle.
Claim 2
Dependent Claim
200 words
A data processing system comprising a) a data input for receiving sequential data units; b) a data output; c) a memory coupled between the data input and the data output and having a plurality of memory locations, for buffering a respective next data unit for the duration of a respective next time delay in a recurrent cycle of time delays; d) a memory address generator coupled to the memory for generating for each respective memory location a respective sequence of time slots, wherein i) each respective time slot starts with an associated write instruction for the respective memory location and terminates with an associated last read instruction for the respective memory location; ii) each respective time slot is representative of the respective time delay; iii) each sequence of time slots is periodic with a period consisting of a first permutation of time slots, the first permutation being indicative of a second permutation of the delay times per cycle; iv) in each first permutation the next time slot is the time slot that has its write instruction executed the earliest with regard to the remaining time slots in the first permutation; and v) the sequences are mutually staggered by one cycle.
Claim 3
Dependent Claim
106 words
A system as in claim 1 wherein the memory address generator comprises: a) a first adder having a first adder output coupled to the memory for providing a next read address to the memory by linearly combining a respective first increment at a first adder input with a preceding read address; b) a second adder having a second adder output coupled to the memory for providing a next write address to the memory by linearly combining a respective second increment with the preceding read address; c) a register element coupled between the first adder input and the first adder output for storing the preceding read address.
Claim 4
Dependent Claim
14 words
A system as in claim 2, wherein the first and second increments are adjustable.
Claim 5
Dependent Claim
106 words
A system as in claim 1 wherein the memory address generator comprises: a) a first adder having a first adder output coupled to the memory for providing a next write address to the memory by linearly combining a respective first increment at a first adder input with a preceding write address; b) a second adder having a second adder output coupled to the memory for providing a next read address to the memory by linearly combining a respective second increment with the preceding write address; c) a register element coupled between the first adder input and the first adder output for storing the preceding write address.
Claim 6
Dependent Claim
14 words
A system as in claim 4, wherein the first and second increments are adjustable.
Claim 7
Dependent Claim
136 words
A system as in claim 1 wherein the memory address generator comprises: a) a reference value generator for at a start of each next cycle generating a next reference value, a series of successive reference values being periodic with the period of the time slot sequence; b) a first adder connected to the reference value generator for receiving the next reference value and for sequentially receiving cyclically recurrent respective first increments for, by linearly combining the reference value with the respective first increment, providing a respective read address to the memory; c) a second adder coupled to the reference value generator for receiving the next reference value and for sequentially receiving cyclically recurrent respective second increments for, by linearly combining the reference value with the respective second increment, providing a respective write address to the memory.
Claim 8
Dependent Claim
15 words
A system as in claim 6 wherein the reference value generator includes a modulo counter.
Claim 9
Dependent Claim
16 words
A system as in claim 6 wherein a leap between two consecutive reference values is adjustable.
Claim 10
Dependent Claim
49 words
System as in claim 6, wherein the memory is adapted to receive at least first and second parallel flows of sequential data units, for each flow the system comprises a respective arrangement of the first adder and the second adder, each arrangement being coupled to the reference value generator.
Claim 11
Dependent Claim
14 words
A system as in claim 6 wherein the first and second increments are adjustable.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-28 | 1995-10-28 | 1996-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-28 | 1999-10-28 | 2000-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-28 | 2003-10-28 | 2004-04-28 | $7700.00 | Window Closed / Lapsed |