Patent US5109186A successfully refreshed from Google Patents.
US5109186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PWM step-down MOSFET regulator
Assignee: Delta Electronic Industry Co Ltd
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Filing: 1990-07-20
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Granted: 1992-04-28
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Expires: 2010-07-20
Abstract
Abstract A regulated step-down switching circuit for a DC-to-DC converter of a power supply includes a pulse width modulation IC, a MOS-FET, a zener diode, a plurality of diodes, capacitors, resistors, and an inductor. The drain of the MOS-FET is connected to a power supply, with its source being connected to a power output lead. The gate of the MOS-FET is connected to one of the transistors of the pulse width modulation IC. A series combination of a diode and capacitor is connected between the source and the drain of the MOS-FET. A second diode and resistor series combination is connected to the junction of the diode and capacitor forming the first series combination and supplies a voltage to the transistor within the pulse width modulation IC as well as being connected to a parallel combination of a zener diode, a capacitor and a diode parallel branches. The other ends of the parallel branches are connected to the power input lead and the pulse width modulation IC. Through these arrangements, when the voltage rises, it will actuate the whole circuit to operate.
Inventors
- 👤 Fan-Yi Lieu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:35
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
225 words
A regulated step-down switching circuit for a DC-to-DC converter of a power supply, said DC-to-DC circuit including a pulse width modulator (PWM) with a switching transistor for receiving a first supply potential and supplying a control signal, said switching circuit comprising: a MOS-FET receiving said first supply potential at a first source/drain and supplying said first supply potential at a second source/drain in response to said control signal applied to a control gate of said MOS-FET; a first diode and a first capacitor connected in series to form a first series circuit, said first series circuit connected between said first and second source/drains of said MOS-FET for supplying a second supply potential at the common junction of said first diode and first capacitor; a second diode and a resistor connected in series to from a second series circuit, said second series circuit having a first terminal connected to said junction of said first diode and first capacitor for receiving said second supply potential and a second terminal connected to said PWM switching transistor for supplying said second supply potential thereto; and a parallel combination of a zener diode, a second capacitor and a third diode, a first node of said parallel combination receiving said first supply potential and a second node supplying said first supply potential to said PWM switching transistor through said parallel combination.
Claim 2
Dependent Claim
225 words
A regulated step-down switching circuit for a DC-to-DC converter of a power supply, said DC-to-DC circuit including a pulse width modulator (PWM) with a switching transistor for receiving a first supply potential and supplying a control signal, said switching circuit comprising: a MOS-FET receiving said first supply potential at a first source/drain and supplying said first supply potential at a second source/drain in response to said control signal applied to a control gate of said MOS-FET; a first diode and a first capacitor connected in series to form a first series circuit, said first series circuit connected between said first and second source/drains of said MOS-FET for supplying a second supply potential at the common junction of said first diode and first capacitor; a second diode and a resistor connected in series to from a second series circuit, said second series circuit having a first terminal connected to said junction of said first diode and first capacitor for receiving said second supply potential and a second terminal connected to said PWM switching transistor for supplying said second supply potential thereto; and a parallel combination of a zener diode, a second capacitor and a third diode, a first node of said parallel combination receiving said first supply potential and a second node supplying said first supply potential to said PWM switching transistor through said parallel combination.
Claim 3
Dependent Claim
32 words
The switching circuit according to claim 1, further comprising a pi network receiving said first supply potential from said MOS-FET second source/drain and supplying said first supply potential at an output terminal.
Claim 4
Dependent Claim
65 words
The switching circuit according to claim 2, wherein said pi network comprises an input node receiving said first supply potential from said MOS-FET second source/drain, a fourth diode connected from said input node to a source of ground potential, an inductor connected from said input node to an output node, and a third capacitor connected from said output node to said source of ground potential.
Claim 5
Dependent Claim
199 words
A regulated step-down circuit for use with a pulse width modulator (PWM) having a first transistor connected to an intermediate node for receiving a first potential, said regulated step-down circuit comprising: an input node for receiving a power supply second potential; a MOS-FET having a first source/drain connected to said input node for receiving said second potential, a control gate receiving a control signal from said first transistor, and a second source/drain connected to an output node for supplying an output potential; a first diode and a first capacitor connected in series forming a common node, said first diode connected in common to said input node and said MOS-FET first source/drain and said first capacitor connected to said MOS-FET second source/drain; a second diode and a resistor connected in series between said common node and said intermediate node; a parallel combination of a zener diode, third diode and second capacitor connected between said input node and said intermediate node for supplying said first potential to said first transistor; and a fourth diode having a first terminal connected in common with said MOS-FET second source/drain and said output node and a second terminal connected to a source of ground potential.
Claim 6
Dependent Claim
199 words
A regulated step-down circuit for use with a pulse width modulator (PWM) having a first transistor connected to an intermediate node for receiving a first potential, said regulated step-down circuit comprising: an input node for receiving a power supply second potential; a MOS-FET having a first source/drain connected to said input node for receiving said second potential, a control gate receiving a control signal from said first transistor, and a second source/drain connected to an output node for supplying an output potential; a first diode and a first capacitor connected in series forming a common node, said first diode connected in common to said input node and said MOS-FET first source/drain and said first capacitor connected to said MOS-FET second source/drain; a second diode and a resistor connected in series between said common node and said intermediate node; a parallel combination of a zener diode, third diode and second capacitor connected between said input node and said intermediate node for supplying said first potential to said first transistor; and a fourth diode having a first terminal connected in common with said MOS-FET second source/drain and said output node and a second terminal connected to a source of ground potential.
Claim 7
Dependent Claim
48 words
The circuit of claim 4, further comprising: an inductor connected between (i) the common connection of said MOS-FET second source/drain and said first terminal of said fourth diode and (ii) said output node; and a third capacitor connected between said output node and said source of ground potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-28 | 1995-10-28 | 1996-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-28 | 1999-10-28 | 2000-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-28 | 2003-10-28 | 2004-04-28 | $7700.00 | Window Closed / Lapsed |