US5108942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master slice integrated circuit having a memory region
Assignee: Mitsubishi Electric Corp
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Filing: 1989-05-03
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Granted: 1992-04-28
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Expires: 2009-05-03
Abstract
Abstract A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.
Inventors
- 👤 Ryou Yonezu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:10
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A method of manufacturing a master slice integrated circuit having a logic circuit and a memory circuit, comprising: a first step of preparing a semiconductor substrate; a second step of forming an array of strip-shaped active areas on said semiconductor substrate to obtain a gate array chip, each of said active areas having a linear array of active elements, said active elements comprising logic circuit elements and memory circuit elements, said active areas being arrayed along a first direction perpendicular to a second along which said linear array extends, wiring-dedicated areas each having wiring capacity selected only from numbers two, three and four in said second direction being provided between respective adjacent pairs of said active areas; a third step of determining a layout of said logic circuit and said memory circuit on said gate array chip; and a fourth step of performing wiring on said gate array chip in accordance with said layout, said active areas being partially employed as wiring areas.
Claim 2
Independent Claim
163 words
A method of manufacturing a master slice integrated circuit having a logic circuit and a memory circuit, comprising: a first step of preparing a semiconductor substrate; a second step of forming an array of strip-shaped active areas on said semiconductor substrate to obtain a gate array chip, each of said active areas having a linear array of active elements, said active elements comprising logic circuit elements and memory circuit elements, said active areas being arrayed along a first direction perpendicular to a second along which said linear array extends, wiring-dedicated areas each having wiring capacity selected only from numbers two, three and four in said second direction being provided between respective adjacent pairs of said active areas; a third step of determining a layout of said logic circuit and said memory circuit on said gate array chip; and a fourth step of performing wiring on said gate array chip in accordance with said layout, said active areas being partially employed as wiring areas.
Claim 3
Independent Claim
239 words
A method of manufacturing a master slice integrated circuit having a logic circuit and a memory circuit, said memory circuit having a plurality of memory blocks, comprising: a first step of preparing a semiconductor substrate; a second step of forming an array of strip-shaped active areas on said semiconductor substrate to obtain a gate array chip, each of said active areas having a plurality of active elements, said active elements comprising logic circuit elements and memory circuit elements, said active areas being arrayed along a first direction perpendicular to a second direction which is a longitudinal direction of said active areas, wiring-dedicated areas each having wiring capacity only selected from numbers two, three and four in said second direction being provided between respective adjacent pairs of said active areas; a third step of determining a layout of said logic circuit and said memory circuit on said gate array chip, including a first process of specifying a region for forming said logic circuit and said memory circuit on said semiconductor substrate, a second process of specifying an end edge of said region extending in said second direction, and a third process of arranging said plurality of memory blocks in said region closely toward said end edge to form an array of said memory blocks; and a fourth step of performing wiring on said gate array chip in accordance with said layout, said active areas being partially employed as wiring areas.
Claim 4
Independent Claim
239 words
A method of manufacturing a master slice integrated circuit having a logic circuit and a memory circuit, said memory circuit having a plurality of memory blocks, comprising: a first step of preparing a semiconductor substrate; a second step of forming an array of strip-shaped active areas on said semiconductor substrate to obtain a gate array chip, each of said active areas having a plurality of active elements, said active elements comprising logic circuit elements and memory circuit elements, said active areas being arrayed along a first direction perpendicular to a second direction which is a longitudinal direction of said active areas, wiring-dedicated areas each having wiring capacity only selected from numbers two, three and four in said second direction being provided between respective adjacent pairs of said active areas; a third step of determining a layout of said logic circuit and said memory circuit on said gate array chip, including a first process of specifying a region for forming said logic circuit and said memory circuit on said semiconductor substrate, a second process of specifying an end edge of said region extending in said second direction, and a third process of arranging said plurality of memory blocks in said region closely toward said end edge to form an array of said memory blocks; and a fourth step of performing wiring on said gate array chip in accordance with said layout, said active areas being partially employed as wiring areas.
Claim 5
Dependent Claim
75 words
A manufacturing method in accordance with claim 2, wherein said array of said memory blocks is provided in a form of memory block rows arrayed from an original line defined by said end edge, and at least each of said memory block rows other than one of said memory block rows has said memory blocks in a maximum number which can be provided within a range of width of said region in said second direction.
Claim 6
Dependent Claim
37 words
A manufacturing method in accordance with claim 3, wherein said array of said memory blocks is obtained by sequentially arranging said memory blocks along an imaginary staggered trace line tracing said memory block rows in alternate directions.
Claim 7
Dependent Claim
80 words
A manufacturing method in accordance with claim 4, wherein said memory blocks are not uniform in size in said first direction, said memory blocks are classified into a plurality of groups in accordance with said size in said first direction, and said array of said memory blocks is obtained by sequentially arranging said memory blocks along said imaginary staggered trace line so that said memory blocks belonging to the same group are sequentially continuous along said imaginary staggered trace line.
Claim 8
Dependent Claim
46 words
A manufacturing method in accordance with claim 5, wherein respective ones of said memory block rows are formed by arranging said memory blocks so that an edge of each said memory block is present on an imaginary straight line which is parallel to said second direction.
Claim 9
Dependent Claim
19 words
A manufacturing method in accordance with claim 6, wherein said memory block rows are not overlapped with each other.
Claim 10
Dependent Claim
32 words
A manufacturing method in accordance with claim 7, wherein sequence of arrangement of said groups along said imaginary staggered trace line is so determined that said memory region is minimized in size.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-28 | 1995-10-28 | 1996-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-28 | 1999-10-28 | 2000-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-28 | 2003-10-28 | 2004-04-28 | $7700.00 | Window Closed / Lapsed |