Patent US5107465A successfully refreshed from Google Patents.
US5107465A
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US
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Asynchronous/synchronous pipeline dual mode memory access circuit and method
Assignee: Cypress Semiconductor Corp
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Filing: 1989-09-13
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Granted: 1992-04-21
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Expires: 2009-09-13
Abstract
Abstract A pipeline memory access circuit has a memory address buffer for buffering memory addresses. The buffer has a first and a second pass gate, and each of the pass gates has a pair of complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided for selectively switching the buffer between an asynchronous and a synchronous mode of operation. The switching apparatus includes circuits for alternately opening and closing the first and second pass gates when the buffer is in its synchronous mode of operation and for simultaneously opening both of the pass gates when the buffer is in its asynchronous mode of operation.
Inventors
- 👤 Jimmy Fung
- 👤 Jiu An
- 👤 David L. Campbell
- 👤 Steven Shyu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:21
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
243 words
An apparatus for selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation is response to an enable control signal having a first and a second logical level, respectively, said buffer having a first and a second pass gate, each of said pass gates having a first and a second CMOS transistor, said apparatus comprising: a first input for receiving clock signals; a second input for receiving said enable control signal; a first output coupled to the gate of the first transistor in each of said first and second pass gates; a second output coupled to the gate of the second transistor in each of said first and second pass gates; and means responsive to said clock signals on said first input and said enable control signal on said second input for providing complementary clock signals on said first and said second outputs, respectively, so as to make conductive the transistors in one of said first and second pass gates while making non-conductive the transistors in the other of said first and second pass gates when said enable control signal is at its first logical level, and a pass gate control signal having the same logical level on both said first and said second outputs for making conductive at least one transistor in each of said first and second pass gates when said enable control signal is at its second logical level.
Claim 2
Independent Claim
243 words
An apparatus for selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation is response to an enable control signal having a first and a second logical level, respectively, said buffer having a first and a second pass gate, each of said pass gates having a first and a second CMOS transistor, said apparatus comprising: a first input for receiving clock signals; a second input for receiving said enable control signal; a first output coupled to the gate of the first transistor in each of said first and second pass gates; a second output coupled to the gate of the second transistor in each of said first and second pass gates; and means responsive to said clock signals on said first input and said enable control signal on said second input for providing complementary clock signals on said first and said second outputs, respectively, so as to make conductive the transistors in one of said first and second pass gates while making non-conductive the transistors in the other of said first and second pass gates when said enable control signal is at its first logical level, and a pass gate control signal having the same logical level on both said first and said second outputs for making conductive at least one transistor in each of said first and second pass gates when said enable control signal is at its second logical level.
Claim 3
Dependent Claim
187 words
An apparatus according to claim 1 wherein said means for providing said complementary clock signals and said pass gate control signal comprises: a first inverter having an input coupled to said first input for receiving clock signals; an AND gate having a first input coupled to an output of said first inverter and a second input coupled to said second input for receiving said enable signal; a second inverter having an input coupled to said second input for receiving said enable signal; and a NOR gate having a first input coupled to an output of said AND gate and a second input coupled to an output of said second inverter, said AND gate providing on an output thereof a first one of said complementary clock signals and said NOR gate providing on an output thereof a second one of said complementary clock signals when said enable signal is at its first logical level, and both said AND gate and said NOR gate providing on the outputs thereof said pass gate control signal having the same logical level when said enable signal is at its second logical level.
Claim 4
Dependent Claim
34 words
An apparatus according to claim 2 further comprising a pair of inverters having inputs respectively coupled to the outputs of said AND gate and said NOR gate for inverting the outputs of said gates.
Claim 5
Independent Claim
153 words
A method of selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation, said buffer having a first and a second pass gate, each of said pass gates having a pair of CMOS transistors, said method comprising the steps of: providing on the gates of each pair of transistors in each of said pass gates complementary clock signals for making conductive the transistors in one of said pairs of gates while making non-conductive the transistors in the other of said pairs of gates when said buffer is in its synchronous mode of operation; and providing on the gates of each pair of transistors in each of said pass gates a control signal having a predetermined logical level for simultaneously making conductive at least one transistor in each of said pairs of transistors when said buffer is in its asynchronous mode of operation.
Claim 6
Independent Claim
153 words
A method of selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation, said buffer having a first and a second pass gate, each of said pass gates having a pair of CMOS transistors, said method comprising the steps of: providing on the gates of each pair of transistors in each of said pass gates complementary clock signals for making conductive the transistors in one of said pairs of gates while making non-conductive the transistors in the other of said pairs of gates when said buffer is in its synchronous mode of operation; and providing on the gates of each pair of transistors in each of said pass gates a control signal having a predetermined logical level for simultaneously making conductive at least one transistor in each of said pairs of transistors when said buffer is in its asynchronous mode of operation.
Claim 7
Dependent Claim
77 words
A method according to claim 4 wherein said step of providing said complementary clock signals comprises providing, in response to a clock signal and an enable signal having a first and a second logical level, said complementary clock signals when said enable signal is at its first logical level, and said step of providing said control signal comprises providing said control signal having said predetermined logical level when said enable signal is at its second logical level.
Claim 8
Dependent Claim
29 words
A method according to claim 5 wherein said predetermined logical level of said control signal is selected from one of a logical low level of a logical high level.
Claim 9
Independent Claim
323 words
An apparatus for selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous an da synchronous mode of operation, said buffer having a first and a second pass gate, each of said pass gates having a pair of CMOS transistors, said apparatus comprising: means for providing on the gates of each pair of transistors in each of said pass gates complementary clock signals for making conductive the transistors in one of said pairs of gates while making non-conductive the transistors in the other of said pairs of gates when said buffer is in its synchronous mode of operation and for simultaneously providing on the gates of each pair of transistors in each of said pass gates a control signal having a predetermined logical level for simultaneously making conductive at least one transistor in each of said pass gates when said buffer is in its asynchronous mode of operation, said means for providing including: a first inverter having an input coupled to a source of clock signals; an AND gate having a first input coupled to an output of said first inverter and a second input coupled to a source of an enable signal having a first and a second logical level; a second inverter having an input coupled to said source of said enable signal; and a NOR gate having a first input coupled to an output of said AND gate and a second input coupled to an output of said second inverter, said AND gate providing on said output thereof a first one of said complementary clock signals and said NOR gate providing on an output thereof a second one of said complementary clock signals when said enable signal is at its first logical level, and both said AND gate and said NOR gate providing on the outputs thereof said control signal having said predetermined logical level when said enable signal is at its second logical level.
Claim 10
Independent Claim
323 words
An apparatus for selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous an da synchronous mode of operation, said buffer having a first and a second pass gate, each of said pass gates having a pair of CMOS transistors, said apparatus comprising: means for providing on the gates of each pair of transistors in each of said pass gates complementary clock signals for making conductive the transistors in one of said pairs of gates while making non-conductive the transistors in the other of said pairs of gates when said buffer is in its synchronous mode of operation and for simultaneously providing on the gates of each pair of transistors in each of said pass gates a control signal having a predetermined logical level for simultaneously making conductive at least one transistor in each of said pass gates when said buffer is in its asynchronous mode of operation, said means for providing including: a first inverter having an input coupled to a source of clock signals; an AND gate having a first input coupled to an output of said first inverter and a second input coupled to a source of an enable signal having a first and a second logical level; a second inverter having an input coupled to said source of said enable signal; and a NOR gate having a first input coupled to an output of said AND gate and a second input coupled to an output of said second inverter, said AND gate providing on said output thereof a first one of said complementary clock signals and said NOR gate providing on an output thereof a second one of said complementary clock signals when said enable signal is at its first logical level, and both said AND gate and said NOR gate providing on the outputs thereof said control signal having said predetermined logical level when said enable signal is at its second logical level.
Claim 11
Dependent Claim
34 words
An apparatus according to claim 7 further comprising a pair of inverters having inputs respectively coupled to the outputs of said AND gate and said NOR gate for inverting the outputs of said gates.
Claim 12
Independent Claim
344 words
A method of selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation, said buffer having a first and a second pass gate, each of said pass gates having a pair of CMOS transistors, said method comprising the steps of: providing on the gates of each pair of transistors in each of said pass gates complementary clock signals for making conductive the transistors in one of said pairs of gates while making non-conductive the transistors in the other of said pairs of gates when said buffer is in its synchronous mode of operation; and providing on the gates of each pair of transistors in each of said pass gates a control signal having a predetermined logical level for simultaneously making conductive at least one transistor in each of said pairs of transistors when said buffer is in its asynchronous mode of operation, wherein said step of providing said complementary clock signals and said step of providing said control signal collectively comprise the steps of: providing a first inverter having an input coupled to a source of clock signals; providing an AND gate having a first input coupled to an output of said first inverter and a second input coupled to a source of an enable signal having a first and a second logical level; providing a second inverter having an input coupled to said source of said enable signal; and providing a NOR gate having a first input coupled to an output of said AND gate and a second input coupled to an output of said second inverter, said AND gate providing on said output thereof a first one of said complementary clock signals and said NOR gate providing on an output thereof a second one of said complementary clock signals when said enable signal is at its first logical level, and both said AND gate and said NOR gate providing on said outputs thereof said control signal having said predetermined logical level when said enable signal is at its second logical level.
Claim 13
Independent Claim
344 words
A method of selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation, said buffer having a first and a second pass gate, each of said pass gates having a pair of CMOS transistors, said method comprising the steps of: providing on the gates of each pair of transistors in each of said pass gates complementary clock signals for making conductive the transistors in one of said pairs of gates while making non-conductive the transistors in the other of said pairs of gates when said buffer is in its synchronous mode of operation; and providing on the gates of each pair of transistors in each of said pass gates a control signal having a predetermined logical level for simultaneously making conductive at least one transistor in each of said pairs of transistors when said buffer is in its asynchronous mode of operation, wherein said step of providing said complementary clock signals and said step of providing said control signal collectively comprise the steps of: providing a first inverter having an input coupled to a source of clock signals; providing an AND gate having a first input coupled to an output of said first inverter and a second input coupled to a source of an enable signal having a first and a second logical level; providing a second inverter having an input coupled to said source of said enable signal; and providing a NOR gate having a first input coupled to an output of said AND gate and a second input coupled to an output of said second inverter, said AND gate providing on said output thereof a first one of said complementary clock signals and said NOR gate providing on an output thereof a second one of said complementary clock signals when said enable signal is at its first logical level, and both said AND gate and said NOR gate providing on said outputs thereof said control signal having said predetermined logical level when said enable signal is at its second logical level.
Claim 14
Dependent Claim
38 words
A method according to claim 9 further comprising a step of providing a pair of inverters having inputs respectively coupled to the outputs of said AND gate and said NOR gate for inverting the outputs of said gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |