US5107199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Temperature compensated resistive circuit
Assignee: Xerox Corp
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Filing: 1990-12-24
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Granted: 1992-04-21
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Expires: 2010-12-24
Abstract
Abstract The present invention is directed to circuitry which uses a reference voltage and a reference current to produce a resistance which stays essentially constant even when the temperature of the device varies. The circuitry of a preferred embodiment consists of a resistor and a n-channel FET. The source of the FET is connected to ground, and the drain is connected to one terminal of the resistor. The other terminal of the resistor is connected to a reference current source and to the noninverting terminal of an operation amplifier. The inverting terminal of the operational amplifier is connected to a reference voltage. The output of the operational amplifier is connected to the gate of the FET. The value of the resistor is chosen such that the voltage drop across the FET (I.e., V ds ) is small so that the FET operates in the linear region. A resistive element is composed of the resistor and the on-resistance of the FET. the resistance of the resistive element is held constant by means of a feedback loop from the operational amplifier.
Inventors
- 👤 Tuan A. Vo
- 👤 Mohammed M. Mojaradi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:23
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/561; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
106 words
A temperature compensated resistive circuit, comprising: a reference voltage; a reference current; a resistor having first and second terminals, said first terminal being connected to said reference current; a first n-channel FET having its source connected to ground and its drain connected to said second terminal of said resistor, said first n-channel FET operating in its linear region; a second n-channel FET having its source connected to ground; and an operational amplifier having its inverting terminal connected to said reference voltage, its noninverting terminal connected to said first terminal of said resistor, and its output connected to the gates of said first and second n-channel FETs.
Claim 2
Dependent Claim
106 words
A temperature compensated resistive circuit, comprising: a reference voltage; a reference current; a resistor having first and second terminals, said first terminal being connected to said reference current; a first n-channel FET having its source connected to ground and its drain connected to said second terminal of said resistor, said first n-channel FET operating in its linear region; a second n-channel FET having its source connected to ground; and an operational amplifier having its inverting terminal connected to said reference voltage, its noninverting terminal connected to said first terminal of said resistor, and its output connected to the gates of said first and second n-channel FETs.
Claim 3
Dependent Claim
116 words
A temperature compensated resistive circuit supplied with a voltage V DD , comprising: a reference voltage; a reference current; a resistor having first and second terminals, said first terminal being connecting to said reference current; a first p-channel FET having its source connected to V DD and its drain connected to said second terminal of said resistor, said first p-channel FET operating in its linear region; a second p-channel FET having its source connected to V dd ; and an operational amplifier having its inverting terminal connected to said reference voltage, its noninverting terminal connected to said first terminal of said resistor, and its output connected to the gates of said first and second p-channel FETs.
Claim 4
Dependent Claim
116 words
A temperature compensated resistive circuit supplied with a voltage V DD , comprising: a reference voltage; a reference current; a resistor having first and second terminals, said first terminal being connecting to said reference current; a first p-channel FET having its source connected to V DD and its drain connected to said second terminal of said resistor, said first p-channel FET operating in its linear region; a second p-channel FET having its source connected to V dd ; and an operational amplifier having its inverting terminal connected to said reference voltage, its noninverting terminal connected to said first terminal of said resistor, and its output connected to the gates of said first and second p-channel FETs.
Claim 5
Dependent Claim
40 words
The resistive circuit of claim 1, wherein the resistive of said resistor is chosen such that the voltage drop between the source and drain of said first n-channel FET causes said first n-channel FET to operate in its linear region.
Claim 6
Dependent Claim
40 words
The resistive circuit of claim 2, wherein the resistance of said resistor is chosen such that the voltage drop between the source and drain of said first p-channel FET causes said first p-channel FET to operate in its linear region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |