High voltage bipolar transistor in BiCMOS

Claim 1

A process for forming bipolar transistors and complementary field effect transistors in a common substrate, comprising the steps of: providing said substrate having a P conductivity type and having an N-channel transistor area, a P-channel transistor area and a bipolar transistor area; forming buried N type layers spaced from a surface of said substrate in said P-channel transistor area and said bipolar transistor area; forming a buried P type layer spaced from said surface of said substrate in said N-channel area; forming an N well in said P-channel transistor area extending from said buried N type layer to said surface; forming P wells in said N-channel transistor area and said bipolar transistor area, said P well extending from said buried P type layer in said N-channel transistor area to said surface and said P well extending from said buried N type layer in said bipolar transistor area to said surface; forming a P base contact region and a P source and P drain by introducing dopant atoms into said P well in said bipolar transistor area and into said N well of said P-channel transistor area; forming an N emitter in said bipolar transistor area by introducing dopant atoms into said P well in said bipolar transistor area; forming an N source and an N drain in said N-channel transistor area by introducing dopant atoms into said P well in said N-channel transistor area; and forming gates controlling conduction between said sources and drains in said N-channel transistor area and said P-channel transistor area,