Systolic array for modular multiplication

Claim 2

A circuit for performing a modular reduction comprising a sequence of connected cells C i , i=1, . . . , n each of said cells C i comprising: a first input for serially receiving a binary number M i-1 and a second input for serially receiving an n-bit modulus N, adding means for serially performing binary addition to form the binary number M i ←M i-1 +NM 0 i-1 , wherein M 0 i-1 is the least significant bit of M i-1 , means for causing a one-bit shift-right operation on said binary number M i , and an output for serially outputting said binary number M i , wherein the first input of the first cell C 1 in said sequence receives a binary number M 0 , wherein the output of cell C i , i=1, . . . , n-1, is the binary number M i and is connected to said first input of the next adjacent cell, and wherein the output of said last cell C n in said sequence outputs a binary number M n which is equal to M 0 R 31 1 (mod N), where R=2 n .

Claim 3

The circuit of claim 1 wherein said circuit further includes subtraction means connected to said output of said last cell for subtracting N from M n if M n ≧2 n .

Claim 4

The circuit of claim 1 wherein the output of each cell C i in said sequence except the last cell is connected to the first input of the next succeeding cell in said sequence.

Claim 5

The circuit of claim 1 wherein said means for causing a one-bit shift-right operation comprises means for insuring that the first bit of M i is a "zero".

Claim 6

The circuit of claim 1 wherein said first input of said first cell C 1 in said sequence receives said binary number M 0 from a systolic array for performing ordinary multiplication.

Claim 7

A circuit for performing modular reduction comprising a first systolic array for performing ordinary multiplication, and a second systolic array for performing a modular reduction on a product produced by said first systolic array, said second systolic array comprising a sequence of cells C i , i=1, . . . , n, each of said cells C i except the first cell having a first input for serially receiving a binary number M i-1 from the preceding cell in the sequence, each of said cells having a second input for receiving an n-bit modulus N, and each of said cells having serial adder means for performing the addition M i-1 +NM 0 i-1 , where M 0 i-1 is the least significant bit in M i-1 , to form the binary number M i , wherein the first cell in said sequence has an input for receiving a binary number M 0 to be modularly reduced, each of said cells has an output, and each of said cells, except the last in said sequence, has its output connected to said first input of the next adjacent cell.

Claim 8

A circuit for performing modular reduction comprising a first systolic array for performing ordinary multiplication, and a second systolic array for performing a modular reduction on a product produced by said first systolic array, said second systolic array comprising a sequence of cells C i , i=1, . . . , n, each of said cells C i except the first cell having a first input for serially receiving a binary number M i-1 from the preceding cell in the sequence, each of said cells having a second input for receiving an n-bit modulus N, and each of said cells having serial adder means for performing the addition M i-1 +NM 0 i-1 , where M 0 i-1 is the least significant bit in M i-1 , to form the binary number M i , wherein the first cell in said sequence has an input for receiving a binary number M 0 to be modularly reduced, each of said cells has an output, and each of said cells, except the last in said sequence, has its output connected to said first input of the next adjacent cell.

Claim 9

The circuit of claim 6 wherein said binary number M 0 is received at the input of the first cell from the first systolic array.

Claim 10

The circuit of claim 6 wherein said first systolic array is Atrubin's array.

Claim 11

The circuit of claim 6 wherein each cell C i in said second systolic array includes means for insuring that the first bit of M i is a "zero".

Claim 12

The circuit of claim 6 wherein a subtractor circuit is connected to an output the last cell in said second systolic array for subtracting N from M n if M n ≧2 n .