Patent US5101369A successfully refreshed from Google Patents.
US5101369A
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Digital filter capable of sample rate alteration
Assignee: Yamaha Corp
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Filing: 1989-11-21
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Granted: 1992-03-31
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Expires: 2009-11-21
Abstract
Abstract A digital filter performs a predetermined arithmetic operation on input digital data inputted thereto in time-series manner by the predetermined first sampling period to thereby generate output digital data corresponding to a second sampling frequency which is N (where N denotes an integral number) times larger than the predetermined first sampling frequency. This digital filter provides a synchronizing signal generating circuit and an operation control circuit. The synchronizing signal generating circuit detects the predetermined first sampling period of the input digital data to thereby generate a synchronizing signal having the second sampling frequency. The operation control circuit is activated by its internal clock which is asynchronous with the input digital data. This operation control circuit starts to perform its operation processes when the synchronizing signal is supplied thereto, thereafter it terminates the operation processes when a predetermined step number is completed.
Inventors
- 👤 Junji Torii
- 👤 Akira Usui
- 👤 Lenichi Takeuchi
- 👤 Masamitsu Yamamura
- 👤 Yusuke Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:54
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0621; H03H17/0628
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
83 words
A digital signal processing circuit comprising: (a) operation means for performing a specified number of operation processes during a predetermined sampling period; (b) detecting means for detecting an input signal indicative of said predetermined sampling period, and for initiating performance of said operation processes by said operation means; and (c) control means responsive to said detecting means, and communicable with said operation means for terminating performance of said operation processes by said operation means when said specified number of operation processes is completed.
Claim 2
Dependent Claim
83 words
A digital signal processing circuit comprising: (a) operation means for performing a specified number of operation processes during a predetermined sampling period; (b) detecting means for detecting an input signal indicative of said predetermined sampling period, and for initiating performance of said operation processes by said operation means; and (c) control means responsive to said detecting means, and communicable with said operation means for terminating performance of said operation processes by said operation means when said specified number of operation processes is completed.
Claim 3
Dependent Claim
143 words
A digital filter comprising: (a) means for performing a predetermined arithmetic operation having a predetermined step number, on time series inputted digital data during a predetermined first sampling period to generate output digital data corresponding to a second sampling frequency which is N (where N is an integer) times larger than a predetermined first sampling frequency corresponding to said first sampling period; (b) a synchronizing signal generating means for generating a synchronizing signal having said second sampling frequency in response to said predetermined first sampling period of said inputted digital data; and (c) an operation control means activated by an internal clock which is asynchronous with said inputted digital data, for initiating operation processes in response to said synchronizing signal generated by said synchronizing signal generating means, said operation control means terminating said operation processes upon a completion of said predetermined step number.
Claim 4
Dependent Claim
143 words
A digital filter comprising: (a) means for performing a predetermined arithmetic operation having a predetermined step number, on time series inputted digital data during a predetermined first sampling period to generate output digital data corresponding to a second sampling frequency which is N (where N is an integer) times larger than a predetermined first sampling frequency corresponding to said first sampling period; (b) a synchronizing signal generating means for generating a synchronizing signal having said second sampling frequency in response to said predetermined first sampling period of said inputted digital data; and (c) an operation control means activated by an internal clock which is asynchronous with said inputted digital data, for initiating operation processes in response to said synchronizing signal generated by said synchronizing signal generating means, said operation control means terminating said operation processes upon a completion of said predetermined step number.
Claim 5
Dependent Claim
142 words
A digital filter comprising: (a) means for performing an arithmetic operation on time-series inputted digital data during a predetermined first sampling period to generate output digital data synchronous with a second sampling frequency which is N (where N is an integer) times larger than a predetermined first sampling frequency corresponding to said first sampling period; a timing generating means for detecting said first sampling period of said inputted digital data to thereby generate a start signal having said second sampling frequency; (c) a detecting means for detecting a bit input rate of each bit within said input digital data; and (d) an output means responsive to said start signal generated by said timing generating means, for outputting said output digital data generated by said arithmetic operation performing means and for controlling timing of said outputting in response to said bit input rate.
Claim 6
Dependent Claim
142 words
A digital filter comprising: (a) means for performing an arithmetic operation on time-series inputted digital data during a predetermined first sampling period to generate output digital data synchronous with a second sampling frequency which is N (where N is an integer) times larger than a predetermined first sampling frequency corresponding to said first sampling period; a timing generating means for detecting said first sampling period of said inputted digital data to thereby generate a start signal having said second sampling frequency; (c) a detecting means for detecting a bit input rate of each bit within said input digital data; and (d) an output means responsive to said start signal generated by said timing generating means, for outputting said output digital data generated by said arithmetic operation performing means and for controlling timing of said outputting in response to said bit input rate.
Claim 7
Dependent Claim
132 words
A digital filter comprising: (a) serial-to-parallel converting means for converting first serial data inputted thereto into first parallel data, said first serial data having a predetermined sampling frequency; (b) synchronizing signal generating means for generating a synchronizing signal having a frequency N times (where N is an integer) larger than said predetermined sampling frequency based on said first serial data; (c) operation means responsive to a clock which is asynchronous with said first serial data, for operating upon said first parallel data with a corresponding coefficient to thereby generate second parallel data indicative of an operation result in response to said synchronizing signal; and (d) parallel-to-serial converting means for converting said second parallel data into second serial data corresponding to said frequency which is N times larger than said predetermined sampling frequency.
Claim 8
Dependent Claim
132 words
A digital filter comprising: (a) serial-to-parallel converting means for converting first serial data inputted thereto into first parallel data, said first serial data having a predetermined sampling frequency; (b) synchronizing signal generating means for generating a synchronizing signal having a frequency N times (where N is an integer) larger than said predetermined sampling frequency based on said first serial data; (c) operation means responsive to a clock which is asynchronous with said first serial data, for operating upon said first parallel data with a corresponding coefficient to thereby generate second parallel data indicative of an operation result in response to said synchronizing signal; and (d) parallel-to-serial converting means for converting said second parallel data into second serial data corresponding to said frequency which is N times larger than said predetermined sampling frequency.
Claim 9
Dependent Claim
95 words
A digital filter according to claim 4 further comprising: bit clock generating means for generating and transmitting bit clocks to said parallel-to-serial converting means so that bits of said second serial data are outputted from said parallel-to-serial means based on said bit clocks, wherein a number of said bit clocks is responsive to a change-over signal transmitted thereto such that a bit number of said second serial data can be changed with reference to said first serial data by adding one or more extension bits obtained from said operation means to said second parallel data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-31 | 1995-09-30 | 1996-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-31 | 1999-09-30 | 2000-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-31 | 2003-09-30 | 2004-03-31 | $7700.00 | Window Closed / Lapsed |