Advanced charge detection amplifier for high performance image sensors

Claim 2

A charge detection amplifier circuit, comprising: an input terminal for receiving an input signal; an output terminal for impressing an amplification of said input signal; a single ended amplification stage coupled to said input terminal for amplifying said input signal; a balance circuit coupled to an output node of said single ended amplification stage and providing an additional bias current to said single ended amplification stage in response to a voltage applied to a balance circuit input terminal; and a buffer stage coupled to said output node of said single ended amplification stage for providing increased current driving capability to said output terminal.

Claim 3

The amplifier circuit of claim 1, further comprising a capacitive element coupled between said output node of said amplification stage and said input terminal for providing feedback.

Claim 4

The amplifier circuit of claim 2, further comprising a reset switch connected across said capacitive element.

Claim 5

The amplifier circuit of claim 1 wherein said amplification stage, said balance circuit, and said buffer stage are fabricated on the same semiconductor substrate.

Claim 6

The amplifier circuit of claim 1, wherein said amplification stage and said balance circuit are comprised of: a first transistor having a first gate coupled to said input terminal, a first source coupled to a first node, and a first drain coupled to said output node; a second transistor having a second gate coupled to said input terminal, a second drain coupled to said output node, and a second source coupled to a second node; a third transistor having a third gate coupled to said output node, a third source coupled to said first node, and a third drain coupled to a first voltage source; a fourth transistor having a fourth gate coupled to said output node, a fourth source coupled to a second voltage source, and a fourth drain coupled to said second node; a fifth transistor having a fifth gate coupled to said first voltage source, a fifth source coupled to said second voltage source, and a fifth drain coupled to said first node; a sixth transistor having a sixth gate coupled to said second voltage source, a sixth drain coupled to said second node, and a sixth source coupled to said first voltage source; a seventh transistor having a seventh gate coupled to said balance circuit input terminal, a seventh drain coupled to said first node, and a seventh source coupled to said output node; and an eighth transistor having an eighth gate coupled to said balance circuit input terminal, an eighth source coupled to said second node, and an eighth drain coupled to said output node.

Claim 7

The amplifier circuit of claim 1 wherein said buffer stage is a dual stage source follower circuit.

Claim 8

The amplifier circuit of claim 1 wherein said voltage applied to said balance circuit input terminal is internally generated within said balance circuit.

Claim 9

The amplifier circuit of claim 5 wherein all said transistors are CMOS transistors.

Claim 10

The amplifier circuit of claim 7, wherein said amplification stage and said balance circuit are comprised of: a first transistor having a first gate coupled to said input terminal, a first source coupled to a first node, and a first drain coupled to said output node; a second transistor having a second gate coupled to said input terminal, a second drain coupled to said output node, and a second source coupled to a second node; a third transistor having a third gate coupled to said output node, a third source coupled to said first node, and a third drain coupled to a first voltage source; a fourth transistor having a fourth gate coupled to said output node, a fourth source coupled to a second voltage source, and a fourth drain coupled to said second node; a fifth transistor having a fifth gate coupled to said first voltage source, a fifth source coupled to said second voltage source, and a fifth drain coupled to said first node; a sixth transistor having a sixth gate coupled to said second voltage source, a sixth drain coupled to said second node, and a sixth source coupled to said first voltage source; a seventh transistor having a seventh gate coupled to a third node, a seventh drain coupled to said first node, and a seventh source coupled to said output node; and an eighth transistor having an eighth gate coupled to said third node, an eighth source coupled to said second node, and an eighth drain coupled to said output node. a ninth transistor having a ninth gate coupled to a fourth node, a ninth source coupled to a second voltage source, and a ninth drain coupled to said third node; a tenth transistor having a tenth gate coupled to said fourth node, a tenth source coupled to said first voltage source, and a tenth drain coupled to said third node; a first resistor coupled between said fourth node and said second voltage source; a second resistor coupled between said fourth node and said first voltage source; and a third resistor coupled between said third node and said fourth node.

Claim 13

The method of claim 10 including the further step of generating said control voltage within said balance circuit.

Claim 14

The method of claim 10, including the further step of coupling a storage element across said amplification stage to provide feedback of said output signal to said input signal.

Claim 15

The method of claim 12, including the further step of coupling a reset switch across said capacitive element.

Claim 16

An image sensor including a charge detection amplifier wherein said amplifier comprises: an input terminal for receiving an input signal; an output terminal for impressing an amplification of said input signal; a single ended amplification stage coupled to said input terminal for amplifying said input signal; a balance circuit coupled to an output node of said single ended amplification stage and providing an additional bias current to said single ended amplification stage in response to a voltage applied to a balance circuit input terminal; and a buffer stage coupled to said output node of said single ended amplification stage for providing increased current driving capability to said output terminal.

Claim 17

An image sensor including a charge detection amplifier wherein said amplifier comprises: an input terminal for receiving an input signal; an output terminal for impressing an amplification of said input signal; a single ended amplification stage coupled to said input terminal for amplifying said input signal; a balance circuit coupled to an output node of said single ended amplification stage and providing an additional bias current to said single ended amplification stage in response to a voltage applied to a balance circuit input terminal; and a buffer stage coupled to said output node of said single ended amplification stage for providing increased current driving capability to said output terminal.