CMOS type input buffer circuit for semiconductor device and semiconductor device with the same

Claim 2

A CMOS type input buffer circuit for a semiconductor device, comprising: a CMOS inverter comprising a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, wherein said when said semiconductor device is in an ordinary operational mode where it operates by a main power supply, said first switching element is turned ON, and when said semiconductor device is in a backup mode where it operates by a backup battery, said first switching element is turned OFF, and wherein said first switching element is connected between said CMOS inverter and ground, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element.

Claim 3

A circuit as set forth in claim 1, wherein a second switching element is connected in parallel with said first transistor, the backup mode signal outputted at the time of said backup mode being applied to a control terminal of said second switching element.

Claim 4

A circuit as set forth in claim 2, wherein said first switching element is comprised of an N-channel transistor, said second switching element being comprised of a P-channel transistor, respective control terminals of said first and second switching elements being commonly connected.

Claim 5

A CMOS type input buffer circuit for a semiconductor device, comprising: a CMOS inverter comprising a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, wherein when said semiconductor device is in an ordinary operational mode where it operates by a main power supply, said first switching element is turned ON, and when said semiconductor device is in a backup mode where it operates by a backup battery, said first switching element is turned OFF, wherein said first switching element is connected between said CMOS inverter and said power supply terminal, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element; and wherein a second switching element is connected in parallel with said second transistor, the backup mode signal outputted at the time of said backup mode being applied to a control terminal of said second switching element.

Claim 6

A CMOS type input buffer circuit for a semiconductor device, comprising: a CMOS inverter comprising a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, wherein when said semiconductor device is in an ordinary operational mode where it operates by a main power supply, said first switching element is turned ON, and when said semiconductor device is in a backup mode where it operates by a backup battery, said first switching element is turned OFF, wherein said first switching element is connected between said CMOS inverter and said power supply terminal, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element; and wherein a second switching element is connected in parallel with said second transistor, the backup mode signal outputted at the time of said backup mode being applied to a control terminal of said second switching element.

Claim 7

A circuit as set forth in claim 4, wherein said first switching element is comprised of a P-channel transistor, said second switching element being comprised of an N-channel transistor, respective control terminals of said first and second switching elements being commonly connected.

Claim 8

A semiconductor device, comprising: a main power supply for delivering a power at the time of an ordinary operational mode; a backup battery for delivering a power at the time of a battery backup mode; a main power supply ON/OFF signal detection circuit for outputting an ON/OFF signal corresponding to ON/OFF of said main power supply; a first circuit operative by a power delivered from said main power supply at the time of said ordinary operational mode to output a signal; and a second circuit wherein when said semiconductor device is in said ordinary operational mode, said second circuit is supplied with a power from said main power supply, and when an output from said first circuit is applied thereto, said second circuit is operated in dependency upon said output, and wherein when said semiconductor device is in said backup mode, said second circuit is operated by a power delivered from said backup battery at the time of said backup mode, said second circuit including a CMOS type input buffer circuit to which an output from said first circuit is applied, said CMOS type input buffer circuit comprising: a CMOS inverter including a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, whereby when said semiconductor device is in the ordinary operational mode where it operates by said main power supply, said switching element is turned ON, and when said semiconductor device is in the backup mode where it operates by said backup battery, said switching element is turned OFF, and wherein said first switching element is connected between said CMOS inverter and ground, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element.

Claim 9

A semiconductor device, comprising: a main power supply for delivering a power at the time of an ordinary operational mode; a backup battery for delivering a power at the time of a battery backup mode; a main power supply ON/OFF signal detection circuit for outputting an ON/OFF signal corresponding to ON/OFF of said main power supply; a first circuit operative by a power delivered from said main power supply at the time of said ordinary operational mode to output a signal; and a second circuit wherein when said semiconductor device is in said ordinary operational mode, said second circuit is supplied with a power from said main power supply, and when an output from said first circuit is applied thereto, said second circuit is operated in dependency upon said output, and wherein when said semiconductor device is in said backup mode, said second circuit is operated by a power delivered from said backup battery at the time of said backup mode, said second circuit including a CMOS type input buffer circuit to which an output from said first circuit is applied, said CMOS type input buffer circuit comprising: a CMOS inverter including a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, whereby when said semiconductor device is in the ordinary operational mode where it operates by said main power supply, said switching element is turned ON, and when said semiconductor device is in the backup mode where it operates by said backup battery, said switching element is turned OFF, and wherein said first switching element is connected between said CMOS inverter and ground, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element.

Claim 10

A semiconductor device as set forth in claim 6, wherein a second switching element is connected in parallel with said first transistor, the backup mode signal outputted at the time of said backup mode being applied to a control terminal of said second switching element.

Claim 11

A semiconductor device as set forth in claim 7, wherein said first switching element is comprised of an N-channel transistor, said second switching element being comprised of a P-channel transistor, respective control terminals of said first and second switching elements being commonly connected.

Claim 12

A semiconductor device, comprising: a main power supply for delivering a power at the time of an ordinary operational mode; a backup battery for delivering a power at the time of a battery backup mode; a main power supply ON/OFF signal detection circuit for outputting an ON/OFF signal corresponding to ON/OFF of said main power supply; a first circuit operative by a power delivered from said main power supply at the time of said ordinary operational mode to output a signal; and a second circuit wherein when said semiconductor device is in said ordinary operational mode, said second circuit is supplied with a power from said main power supply, and when an output from said first circuit is applied thereto, said second circuit is operated in dependency upon said output, and wherein when said semiconductor device is in said backup mode, said second circuit is operated by a power delivered from said backup battery at the time of said backup mode, said second circuit including a CMOS type input buffer circuit to which an output from said first circuit is applied, said CMOS type input buffer circuit comprising: a CMOS inverter including a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, whereby when said semiconductor device is in the ordinary operational mode where it operates by said main power supply, said switching element is turned ON, and when said semiconductor device is in the backup mode where it operates by said backup battery, said switching element is turned OFF, wherein said first switching element is connected between said CMOS inverter and said power supply terminal, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element and wherein a second switching element is connected in parallel with said second transistor, the backup mode signal outputted at the time of said backup mode being applied to a control terminal of said second switching element.

Claim 13

A semiconductor device, comprising: a main power supply for delivering a power at the time of an ordinary operational mode; a backup battery for delivering a power at the time of a battery backup mode; a main power supply ON/OFF signal detection circuit for outputting an ON/OFF signal corresponding to ON/OFF of said main power supply; a first circuit operative by a power delivered from said main power supply at the time of said ordinary operational mode to output a signal; and a second circuit wherein when said semiconductor device is in said ordinary operational mode, said second circuit is supplied with a power from said main power supply, and when an output from said first circuit is applied thereto, said second circuit is operated in dependency upon said output, and wherein when said semiconductor device is in said backup mode, said second circuit is operated by a power delivered from said backup battery at the time of said backup mode, said second circuit including a CMOS type input buffer circuit to which an output from said first circuit is applied, said CMOS type input buffer circuit comprising: a CMOS inverter including a first transistor of a P-channel and a second transistor of a N-channel connected in series between a power supply terminal and ground; and a first switching element connected to said CMOS inverter, whereby when said semiconductor device is in the ordinary operational mode where it operates by said main power supply, said switching element is turned ON, and when said semiconductor device is in the backup mode where it operates by said backup battery, said switching element is turned OFF, wherein said first switching element is connected between said CMOS inverter and said power supply terminal, a backup mode signal outputted at the time of said backup mode being applied to a control terminal of said first switching element and wherein a second switching element is connected in parallel with said second transistor, the backup mode signal outputted at the time of said backup mode being applied to a control terminal of said second switching element.

Claim 14

A semiconductor device as set forth in claim 9, wherein said first switching element is comprised of a P-channel transistor, and said second switching element being comprised of an N-channel transistor, respective control terminals of said first and second switching elements being commonly connected.