US5099494A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Six channel digital demodulator
Assignee: Unisys Corp
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Filing: 1990-07-26
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Granted: 1992-03-24
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Expires: 2010-07-26
Abstract
Abstract A six channel programmable digital demodulator of the type designed to be manufactured as an integrated circuit with other components comprises a code channel, a level channel and a phase channel each of which includes two accumulate and scale circuits. Each of the accumulate and scale circuits is connected to an I or a Q channel of the data which has been despread after being received from the communications receiver. The outputs of two of the accumulate and scale circuits are applied to a two to one multiplexor which is controlled by a command generator to provide a selectable output defining a clock error signal. The remaining four accumulate and scale circuits are connected to a first four to one multiplexor to provide a selectable output defining a clock error signal. The same four remaining outputs from said accumulate and scale circuits are connected to a second four to one multiplexor having an output defining a carrier error signal.
Inventors
- 👤 Samuel C. Kingston
- 👤 Steven T. Barham
- 👤 Harold L. Simonsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:41
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2332; H04L27/0014; H04L2027/0024; H04L2027/0026; H04L2027/003; H04L2027/0044; H04L2027/0053; H04L2027/0057; H04L2027/0063; H04L2027/0065
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
182 words
A programmable digital demodulator circuit of the type used for processing real (Q) and imaginary (I) process data signals for use in communication receivers, comprising: a code channel despreader, a level channel despreader, a phase channel despreader, said real (I) and the imaginary (Q) process data signals from said communications receiver being coupled to each said despreader, each said despreader having an I and a Q output signal individually connected as inputs to a data rate filter means having six output signals which define three I and three Q channels, a first multiplexor being connected to a pair of I and Q channels to provide a selectable output signal representing a clock error signal, a second multiplexor being connected to the remaining I and Q channels to provide a selectable output signal representing a magnitude level signal, a third multiplexor being connected to said remaining I and Q channels to provide an output signal representing a carrier error signal, and programmable command generators means connected to each of said multiplexors for selecting one of a plurality of inputs for each multiplexor output.
Claim 2
Dependent Claim
182 words
A programmable digital demodulator circuit of the type used for processing real (Q) and imaginary (I) process data signals for use in communication receivers, comprising: a code channel despreader, a level channel despreader, a phase channel despreader, said real (I) and the imaginary (Q) process data signals from said communications receiver being coupled to each said despreader, each said despreader having an I and a Q output signal individually connected as inputs to a data rate filter means having six output signals which define three I and three Q channels, a first multiplexor being connected to a pair of I and Q channels to provide a selectable output signal representing a clock error signal, a second multiplexor being connected to the remaining I and Q channels to provide a selectable output signal representing a magnitude level signal, a third multiplexor being connected to said remaining I and Q channels to provide an output signal representing a carrier error signal, and programmable command generators means connected to each of said multiplexors for selecting one of a plurality of inputs for each multiplexor output.
Claim 3
Dependent Claim
44 words
A programmable digital demodulator as set forth in claim 1 which further includes a decision directed invertor for each multiplexor being connected in the output signal path of each of said multiplexors being connected in the output signal path of each of said multiplexors.
Claim 4
Dependent Claim
24 words
A programmable digital demodulator as set forth in claim 2 wherein each decision directed invertor is individually connected to said programmable command generator means.
Claim 5
Dependent Claim
23 words
A programmable digital demodulator as set forth in claim 1 wherein said data rate filter means comprises programmable accumulate and scale circuit means.
Claim 6
Dependent Claim
34 words
A programmable digital demodulator as set forth in claim 1 which further includes a programmable chip rate filter means having output signals which provide the I and Q input data applied to said despreaders.
Claim 7
Dependent Claim
23 words
A programmable digital demodulator as set forth in claim 5 wherein each said rate filter means comprises a programmable pre-accumulate and scale circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |