Device for correcting errors by a long-distance code

Claim 1

A device for correcting errors of a long-distance code, when decoding a long-distance code capable of correcting errors up to maximum of t words of which one word is composed of w bits, by obtaining a coefficient of each term of an error-position polynomial by setting data words A.sub.(i+j-2) to each element q i ,j of a matrix having t rows and (t+1) columns, where 1≦i≦t, 1≦j≦ t+1, A 0 to A 2t-1 represent syndromes or error positions, and by performing a left-hand elementary transformation over the matrix in order to obtain each coefficient of each term of the error position polynomial or error patterns from syndromes, comprising: memory means having a bit width of (w×t) and t+1) addresses, each of said (t+1) addresses being in one to one correspondence with each column of said matrix, a coefficient calculating circuit having a first multiplying means for multiplying each coefficient in the error-position polynomial by each root in the error-position polynomial corresponding to each coefficient, and an integrating means for integrating sequentially each multiplied value of each coefficient and each root and for detecting whether an integrated value of each multiplied value is 0 or not, operations of said first multiplying means and said integrating means being repeated until the repeated number thereof is equal to the number of words in one correction sequence; an error pattern calculating circuit having a second multiplying means for multiplying power of each of the error positions obtained on the basis of each of coefficient of the error-position polynomial by each root in the error-position polynomial corresponding to power of each of the error-positions in synchronization with the operation of said first multiplying means and said integrating means, and for writing each multiplied value of each root and power of each of the error positions in said memory means when said integrating means detects 0; and an error position calculating means for obtaining the error-positions by utilizing said coefficient calculating circuit of the error-position polynomial and said error pattern calculating circuit, said error position calculating means performing calculating operations in unit of each column by writing and reading in unit of each column a data word of each column of said matrix at each corresponding address position in said memory means.

Claim 2

A device for correcting errors of a long-distance code, when decoding a long-distance code capable of correcting errors up to maximum of t words of which one word is composed of w bits, by obtaining a coefficient of each term of an error-position polynomial by setting data words A.sub.(i+j-2) to each element q i ,j of a matrix having t rows and (t+1) columns, where 1≦i≦t, 1≦j≦ t+1, A 0 to A 2t-1 represent syndromes or error positions, and by performing a left-hand elementary transformation over the matrix in order to obtain each coefficient of each term of the error position polynomial or error patterns from syndromes, comprising: memory means having a bit width of (w×t) and t+1) addresses, each of said (t+1) addresses being in one to one correspondence with each column of said matrix, a coefficient calculating circuit having a first multiplying means for multiplying each coefficient in the error-position polynomial by each root in the error-position polynomial corresponding to each coefficient, and an integrating means for integrating sequentially each multiplied value of each coefficient and each root and for detecting whether an integrated value of each multiplied value is 0 or not, operations of said first multiplying means and said integrating means being repeated until the repeated number thereof is equal to the number of words in one correction sequence; an error pattern calculating circuit having a second multiplying means for multiplying power of each of the error positions obtained on the basis of each of coefficient of the error-position polynomial by each root in the error-position polynomial corresponding to power of each of the error-positions in synchronization with the operation of said first multiplying means and said integrating means, and for writing each multiplied value of each root and power of each of the error positions in said memory means when said integrating means detects 0; and an error position calculating means for obtaining the error-positions by utilizing said coefficient calculating circuit of the error-position polynomial and said error pattern calculating circuit, said error position calculating means performing calculating operations in unit of each column by writing and reading in unit of each column a data word of each column of said matrix at each corresponding address position in said memory means.