US5099453A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Configuration memory for programmable logic device
Assignee: STMicroelectronics lnc USA
•
Filing: 1989-09-29
•
Granted: 1992-03-24
•
Expires: 2009-09-29
Abstract
Abstract A programmable logic integrated circuit device utilizes volatile memory elements such as SRAM for retaining configuration information. A circuit is provided as part of the device for detecting loss of power on a supply input pin. When power loss is detected, a backup voltage supply, packaged with the programmable logic device as a unit, is connected thereto. The backup power is used to supply voltage only to those portions of the device having volatile memory elements containing configuration information. Backup power is not provided to input and output buffers of the device, thereby preventing excess loads being placed upon the backup device because of events which may occur external to the programmable logic device.
Inventors
- 👤 Randy C. Steele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17772; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C16/00; G11C16/02; G11C5/00; G11C5/14; G11C5/141; H03K19/17704; H03K19/1776; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
150 words
A programmable logic integrated circuit device, comprising: a plurality of input/output buffers, wherein said input/output buffers can be individually configured to function as either input or output buffers; a plurality of memory elements for storing configuration information, said configuration information operable to define logic operations to be performed by the integrated circuit device, wherein said plurality of memory elements further includes latches for storing configuration information for said buffers, the configuration information defining the operation of each buffer as an input buffer or an output buffer; a power loss detect circuit connected to a device supply voltage input; and a backup power supply connected to said power loss detect circuit; wherein, when said power loss detect circuit detects a power loss on the supply voltage input, said backup power supply is switched to provide power to said memory elements, and wherein backup power is not supplied to said input/output buffers.
Claim 2
Dependent Claim
150 words
A programmable logic integrated circuit device, comprising: a plurality of input/output buffers, wherein said input/output buffers can be individually configured to function as either input or output buffers; a plurality of memory elements for storing configuration information, said configuration information operable to define logic operations to be performed by the integrated circuit device, wherein said plurality of memory elements further includes latches for storing configuration information for said buffers, the configuration information defining the operation of each buffer as an input buffer or an output buffer; a power loss detect circuit connected to a device supply voltage input; and a backup power supply connected to said power loss detect circuit; wherein, when said power loss detect circuit detects a power loss on the supply voltage input, said backup power supply is switched to provide power to said memory elements, and wherein backup power is not supplied to said input/output buffers.
Claim 3
Dependent Claim
18 words
The device of claim 1, wherein said backup power supply comprises a battery integrally packaged with the device.
Claim 4
Dependent Claim
21 words
The device of claim 1, wherein said plurality of memory elements comprises a random access memory configured to perform logic functions.
Claim 5
Dependent Claim
28 words
The device of claim 3, wherein said plurality of memory elements further comprises random access memory which can be written to and read from during normal device operation.
Claim 6
Dependent Claim
23 words
The device of claim 3, wherein said plurality of memory elements further comprises configuration bits for controlling the operation of programmable switching matrices.
Claim 7
Dependent Claim
116 words
A power supply for a programmable logic device having input/output buffers and volatile memory elements, comprising: a power supply input pin for supplying power to the device; a battery housed with the device as an integral unit; and power loss detect circuitry connected to said input pin and to said battery, wherein the volatile memory elements include bits for configuring at least one of the input/output buffers to operate either for input or for output depending on a value stored in the bit, wherein said battery is electrically connected to the volatile memory elements when power loss is detected by said power loss detect circuitry, and wherein said battery is electrically isolated from the input/output buffers.
Claim 8
Dependent Claim
116 words
A power supply for a programmable logic device having input/output buffers and volatile memory elements, comprising: a power supply input pin for supplying power to the device; a battery housed with the device as an integral unit; and power loss detect circuitry connected to said input pin and to said battery, wherein the volatile memory elements include bits for configuring at least one of the input/output buffers to operate either for input or for output depending on a value stored in the bit, wherein said battery is electrically connected to the volatile memory elements when power loss is detected by said power loss detect circuitry, and wherein said battery is electrically isolated from the input/output buffers.
Claim 9
Dependent Claim
20 words
The supply of claim 6, wherein the volatile memory elements comprise a random access memory configured to perform logic functions.
Claim 10
Dependent Claim
27 words
The supply of claim 7, wherein the volatile memory elements further include configuration bits for programmable switching matrices used to interconnect portions of the random access memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |