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US5099150A
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Circuit block for programmable logic devices, configurable as a user-writable memory or a logic circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1990-08-30
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Granted: 1992-03-24
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Expires: 2010-08-30
Abstract
Abstract A standard logic block, or macrocell, is provided for use on programmable logic devices. The macrocell uses RAM to perform logic functions, and further includes circuitry which allows writing of data to the RAM during use. Each logic block can be configured at programming time to be either a user RAM, allowing the user to write data to such memory during use, or configured as performing logic functions. The contents of macrocells configured as providing logic functions cannot be charged except by reprogramming the device.
Inventors
- 👤 Randy C. Steele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
118 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder; a read buffer connected to said random access memory for reading data output therefrom; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 2
Dependent Claim
118 words
A circuit block for use in programmable logic devices, comprising: a decoder; a random access memory having a plurality of bits addressed by said decoder; a read buffer connected to said random access memory for reading data output therefrom; a write driver connected to said random access memory for inputting data thereto; means for configuring the circuit block to function as user-writable memory or to provide a logic function; and a plurality of input lines into the circuit block, wherein said input lines provide control signals when the circuit block is configured to provide a logic function, and wherein said input lines provide control and data signals when the circuit block is configured to function as user-writable memory.
Claim 3
Dependent Claim
46 words
The circuit block of claim 1, wherein a first subset of said input lines are used to provide data signals when the circuit block is configured to provide a user-writable memory and are not used when the circuit block is configured to provide a logic function.
Claim 4
Dependent Claim
35 words
The circuit block of claim 2, wherein a second subset of said input lines provide control signals when the circuit block is configured either to function as user-writable memory or to provide a logic function.
Claim 5
Dependent Claim
37 words
The circuit block of claim 1, wherein said random access memory provides a plurality of outputs, each corresponding to a column of memory, and wherein said read buffer provides a separate read buffer for each memory column.
Claim 6
Dependent Claim
24 words
The circuit block of claim 4, wherein each column of random access memory has a separate decoder for addressing the bits of the column.
Claim 7
Dependent Claim
21 words
The circuit of claim 5, wherein each column of random access memory further has an independently addressable write driver connected thereto.
Claim 8
Dependent Claim
19 words
The circuit block of claim 4, wherein said memory columns are capable of being configured to provide parallel outputs.
Claim 9
Dependent Claim
18 words
The circuit block of claim 4, wherein said memory has n columns each having m bits of storage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |