Signal processor including programmable logic unit formed of individually controllable output bit producing sections

Claim 1

A signal processor for executing dyadic or monadic and bit-wise operations on operand data presented by an input data bus to produce result data presented to an output data bus in accordance with instruction data presented on an instruction bus, said processor comprising: a programmable logic unit formed of a plurality of logic unit sections, each comprising a logic function block for determining at an output of said block the value of a different bit position of the result data, said logic function block being configured for execution of a logic operation, selectable from a set of logic operations, on one or more input bits in response to first control signals indicative of the logic operation selected from said set; multiplex means responsive to said input data bus for presenting selectable bit positions of said operand data from said input data bus as said input bits to said logic unit sections in response to second control signals indicative of the bit positions of said operand data selected; control means responsive to said instruction bus for presenting said first control signals to the logic function blocks and said second control signals to said multiplex means; and output buffer means for receiving the values of the bit positions of the result data output from said logic unit sections and presenting said values as said result data to said output data bus.