Circuit for and method of controlling output buffer memory

Claim 1

An output control circuit for controlling the reading and writing of data in a frame buffer which stores a plurality of square blocks of words, each word having n bits, in a one-to-one correspondence with a two dimensional output area having m blocks of n words arrayed in X and Y directions, said frame buffer being formed of n memory devices each storing m times n bits, said output control circuit comprising: (a) word address generating means for generating an address for each bit of a word to be accessed in said frame buffer based on a lower bit portion of a X axis address and a lower bit portion of a Y axis address of a bit location of said two dimensional output area and a switching signal indicating the X or Y axis as an access direction; (b) block address and adjacent block address generating means for generating an address of a block of said plurality of blocks based on an upper bit portion of said X axis address and an upper bit portion of said Y axis address and said switching signal and for generating an address of an adjacent block residing adjacent said block in said two dimensional output area in X or Y direction indicated by said switching signal; (c) pattern generating means responsive to said lower bit portions of said X axis and Y axis addresses for generating a mask pattern to determine whether data is to be read from or written into a block or an adjacent block at locations based on a selected bit position identified by the lower bit portions of said X axis and Y axis addresses; (d) access means for controlling said block address and adjacent block address generating means to access both a block and an adjacent block if accessed data bridges said adjacent block as determined by said pattern generating means; (e) read data synthesize means for synthesizing read data based on said pattern generated by said pattern generating means, read data read out of said block and read data read out of said adjacent block, if read data bridges said adjacent block; (f) write data synthesize means for synthesizing received write data based on said pattern generated by said pattern generating means and for writing the synthesized data into said block and an adjacent block if write data bridges said adjacent block; and (g) rotate means for rotating data to provide correspondence between received data and data of said block and said adjacent block by rotation of data based on said lower bit portion of an X axis address and said lower bit portion of a Y axis address of a bit location of said two dimensional output area to be accessed with said switching signal.